MLK-17221 clk: imx8mq: Add shared gate for apbh-dma and gpmi clocks

The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index 0676ffc..3795ced 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -1350,7 +1350,7 @@
                interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
                #dma-cells = <1>;
                dma-channels = <4>;
-               clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>;
+               clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
        };
 
        gpmi: gpmi-nand@33002000{
@@ -1362,7 +1362,7 @@
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "bch";
                clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>,
-                       <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>;
+                       <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
                clock-names = "gpmi_io", "gpmi_bch_apb";
                dmas = <&dma_apbh 0>;
                dma-names = "rx-tx";

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 1582ed7..2f70a5b 100644 (file)
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -30,6 +30,7 @@ static u32 share_count_sai4;
 static u32 share_count_sai5;
 static u32 share_count_sai6;
 static u32 share_count_dcss;
+static u32 share_count_nand;
 
 static struct clk *clks[IMX8MQ_CLK_END];
 
@@ -779,7 +780,8 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
        clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3_div", base + 0x42a0, 0);
        clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4_div", base + 0x42b0, 0);
        clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi_div", base + 0x42f0, 0);
-       clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate4("nand_root_clk", "nand_div", base + 0x4300, 0);
+       clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand_div", base + 0x4300, 0, &share_count_nand);
+       clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus_div", base + 0x4300, 0, &share_count_nand);
        clks[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_div", base + 0x4330, 0, &share_count_sai1);
        clks[IMX8MQ_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1);
        clks[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_div", base + 0x4340, 0, &share_count_sai2);

diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index b5b31e0..9932b52 100644 (file)
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -626,5 +626,7 @@
 #define IMX8MQ_CLK_CLKO2_PRE_DIV               486
 #define IMX8MQ_CLK_CLKO2_DIV                   487
 
-#define IMX8MQ_CLK_END                         488
+#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK  488
+
+#define IMX8MQ_CLK_END                         489
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */