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arm64: imx8-ss-dc1.dtsi: Correct display LPCG clocks in DC1 subsystem
authorLiu Ying <victor.liu@nxp.com>
Fri, 22 Nov 2019 09:54:22 +0000 (17:54 +0800)
committerDong Aisheng <aisheng.dong@nxp.com>
Mon, 14 Dec 2020 03:21:13 +0000 (11:21 +0800)
This patch corrects display LPCG clocks in DC1 subsystem by
s/dc0_disp_lpcg/dc1_disp_lpcg/.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi patch | blob | history

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi
index af6a589..3702975 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi
@@ -468,7 +468,7 @@ dc1_subsys: bus@57000000 {
                         <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
                         <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>,
                         <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>,
-                        <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>;
+                        <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>;
                clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg";
                power-domains = <&pd IMX_SC_R_DC_1>,
                                <&pd IMX_SC_R_DC_1_PLL_0>,