MLK-10009-2 ARM: imx6sx: Add imx6sx pcie related gpr bits definitions
authorRichard Zhu <richard.zhu@freescale.com>
Thu, 16 Oct 2014 06:54:40 +0000 (14:54 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 19:48:39 +0000 (14:48 -0500)
Add imx6sx pcie related gpr bits definitions.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
(cherry picked from commit 991fb25d62e3e2f550f98732f5bc00eeb98f78e3)

include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

index 3d0ff5c..fe95e71 100644 (file)
 #define IMX6Q_GPR12_DEVICE_TYPE                        (0xf << 12)
 #define IMX6Q_GPR12_PCIE_CTL_2                 BIT(10)
 #define IMX6Q_GPR12_LOS_LEVEL                  (0x1f << 4)
+#define IMX6Q_GPR12_LOS_LEVEL_9                        (0x9 << 4)
 
 #define IMX6Q_GPR13_SDMA_STOP_REQ              BIT(30)
 #define IMX6Q_GPR13_CAN2_STOP_REQ              BIT(29)
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK                (0x1 << 26)
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE      (0x1 << 26)
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE     (0x0 << 26)
+#define IMX6SX_GPR5_PCIE_PERST                         BIT(18)
 #define IMX6SX_GPR5_PCIE_BTNRST_RESET                  BIT(19)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK                 (0x3 << 4)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN              (0x0 << 4)
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS                        (0x1 << 1)
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK                        (0x1 << 1)
 
+#define IMX6SX_GPR12_PCIE_PM_TURN_OFF                  BIT(16)
 #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN               BIT(30)
 #define IMX6SX_GPR12_PCIE_RX_EQ_MASK                   (0x7 << 0)
 #define IMX6SX_GPR12_PCIE_RX_EQ_2                      (0x2 << 0)