MLK-11561-1 ARM: imx: enable pcie on imx6sx platforms

enable pcie support on imx6sx platforms.

Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>

diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 39c3f2d..563e9c9 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -14,6 +14,13 @@
        model = "Freescale i.MX6 SoloX Sabre Auto Board";
        compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
 
+       max7310_reset: max7310-reset {
+               compatible = "gpio-reset";
+               reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+               reset-delay-us = <1>;
+               #reset-cells = <0>;
+       };
+
        memory {
                reg = <0x80000000 0x80000000>;
        };
@@ -107,6 +114,34 @@
        };
 };
 
+&i2c3 {
+        clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3_2>;
+       status = "okay";
+
+       max7310_a: gpio@30 {
+               compatible = "maxim,max7310";
+               reg = <0x30>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               resets = <&max7310_reset>;
+       };
+
+       max7310_b: gpio@32 {
+               compatible = "maxim,max7310";
+               reg = <0x32>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               resets = <&max7310_reset>;
+       };
+};
+
+&pcie {
+       reset-gpio = <&max7310_b 3 0>;
+       status = "okay";
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -215,6 +250,13 @@
                        >;
                };
 
+               pinctrl_i2c3_2: i2c3grp-2 {
+                       fsl,pins = <
+                               MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
+                               MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
+                       >;
+               };
+
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index db6a06b..d12c1fd 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -137,6 +137,19 @@
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                };
+
+               reg_pcie: regulator@8 {
+                       compatible = "regulator-fixed";
+                       reg = <8>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_pcie_reg>;
+                       regulator-name = "MPCIE_3V3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio2 1 0>;
+                       regulator-always-on;
+                       enable-active-high;
+               };
        };
 
        sound {
@@ -351,6 +364,13 @@
        };
 };
 
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       reset-gpio = <&gpio2 0 0>;
+       status = "okay";
+};
+
 &pwm3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm3>;
@@ -597,6 +617,18 @@
                        >;
                };
 
+               pinctrl_pcie: pciegrp {
+                       fsl,pins = <
+                               MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
+                       >;
+               };
+
+               pinctrl_pcie_reg: pciereggrp {
+                       fsl,pins = <
+                               MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
+                       >;
+               };
+
                pinctrl_peri_3v3: peri3v3grp {
                        fsl,pins = <
                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 877b966..dfbc6b2 100644 (file)
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -677,9 +677,9 @@
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_pcie: regulator-vddpcie {
+                               reg_pcie_phy: regulator-vddpcie-phy@140 {
                                        compatible = "fsl,anatop-regulator";
-                                       regulator-name = "vddpcie";
+                                       regulator-name = "vddpcie-phy";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1450000>;
                                        anatop-reg-offset = <0x140>;
@@ -795,6 +795,15 @@
                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-parent = <&intc>;
                                fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>;
+                               clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>,
+                                       <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>,
+                                       <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>,
+                                       <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_CSI>,
+                                       <&clks IMX6SX_CLK_VADC>;
+                               clock-names = "gpu3d_core", "ipg", "pxp_axi", "disp_axi", "lcdif1_pix",
+                                               "lcdif_axi", "lcdif2_pix", "csi_mclk";
+                               pcie-phy-supply = <&reg_pcie_phy>;
+                               #power-domain-cells = <1>;
                        };
 
                        iomuxc: iomuxc@020e0000 {
@@ -1368,24 +1377,29 @@
 
                pcie: pcie@0x08000000 {
                        compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
-                       reg = <0x08ffc000 0x4000>; /* DBI */
+                       reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>;
+                       reg-names = "dbi", "config";
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
-                                 /* configuration space */
-                       ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
-                                 /* downstream I/O */
-                                 0x81000000 0 0          0x08f80000 0 0x00010000
-                                 /* non-prefetchable memory */
-                                 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
+                       ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
+                                 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
                        num-lanes = <1>;
-                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
-                                <&clks IMX6SX_CLK_PCIE_AXI>,
+                       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
                                 <&clks IMX6SX_CLK_LVDS1_OUT>,
+                                <&clks IMX6SX_CLK_PCIE_REF_125M>,
                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
-                       clock-names = "pcie_ref_125m", "pcie_axi",
-                                     "lvds_gate", "display_axi";
+                       clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+                       pcie-phy-supply = <&reg_pcie_phy>;
+                       power-domains = <&gpc 2>;
                        status = "disabled";
                };
        };