MLK-15046-11 arm64: dts: fsl-imx8qxp-lpddr4-arm2: add flexcan support

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index 7411b30..49f883e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -43,6 +43,25 @@
                        enable-active-high;
                };
 
+               reg_can_en: regulator-can-gen {
+                       compatible = "regulator-fixed";
+                       regulator-name = "can-en";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_can_stby: regulator-can-stby {
+                       compatible = "regulator-fixed";
+                       regulator-name = "can-stby";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       vin-supply = <&reg_can_en>;
+               };
+
                reg_audio: fixedregulator@0 {
                        compatible = "regulator-fixed";
                        reg = <2>;
@@ -169,6 +188,27 @@
                        >;
                };
 
+               pinctrl_flexcan1: flexcan0grp {
+                       fsl,pins = <
+                               SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX               0x21
+                               SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX               0x21
+                       >;
+               };
+
+               pinctrl_flexcan2: flexcan1grp {
+                       fsl,pins = <
+                               SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX               0x21
+                               SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX               0x21
+                       >;
+               };
+
+               pinctrl_flexcan3: flexcan2grp {
+                       fsl,pins = <
+                               SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX               0x21
+                               SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX               0x21
+                       >;
+               };
+
                pinctrl_lpi2c1: lpi1cgrp {
                        fsl,pins = <
                                SC_P_USB_SS3_TC0_ADMA_I2C1_SCL  0x06000020
@@ -305,6 +345,27 @@
        status = "disabled";
 };
 
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       xceiver-supply = <&reg_can_stby>;
+       status = "okay";
+};
+
+&flexcan2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       xceiver-supply = <&reg_can_stby>;
+       status = "okay";
+};
+
+&flexcan3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan3>;
+       xceiver-supply = <&reg_can_stby>;
+       status = "okay";
+};
+
 &i2c0_csi0 {
        #address-cells = <1>;
        #size-cells = <0>;
@@ -350,6 +411,13 @@
                gpio-controller;
                #gpio-cells = <2>;
        };
+
+       pca9557_b: gpio@19 {
+               compatible = "nxp,pca9557";
+               reg = <0x19>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
 };
 
 &lpuart0 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 3aa4a16..64ce351 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -797,6 +797,45 @@
                power-domains = <&pd_conn_usbotg0>;
        };
 
+       flexcan1: can@5a8d0000 {
+               compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+               reg = <0x0 0x5a8d0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+                        <&clk IMX8QXP_CAN0_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_flexcan0>;
+               status = "disabled";
+       };
+
+       flexcan2: can@5a8e0000 {
+               compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+               reg = <0x0 0x5a8e0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QXP_CAN1_IPG_CLK>,
+                        <&clk IMX8QXP_CAN1_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QXP_CAN1_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_flexcan1>;
+               status = "disabled";
+       };
+
+       flexcan3: can@5a8f0000 {
+               compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+               reg = <0x0 0x5a8f0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QXP_CAN2_IPG_CLK>,
+                        <&clk IMX8QXP_CAN2_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QXP_CAN2_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_flexcan2>;
+               status = "disabled";
+       };
+
        gpio0: gpio@5d080000 {
                compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
                reg = <0x0 0x5d080000 0x0 0x10000>;