/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or
* GNU General Public License for more details.
*/
-/dts-v1/;
-
-#include "fsl-imx8mq.dtsi"
+#include "fsl-imx8mq-evk-fbdev.dts"
/ {
- model = "Freescale i.MX8MQ EVK";
- compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
-
- bcmdhd_wlan_0: bcmdhd_wlan@0 {
- compatible = "android,bcmdhd_wlan";
- bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin";
- bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal";
- };
-
- chosen {
- bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
- stdout-path = &uart1;
- };
-
- regulators {
- compatible = "simple-bus";
+ dcss_drm: dcss@0x32e00000 {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "nxp,imx8mq-dcss";
+ reg = <0x0 0x32e00000 0x0 0x30000>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>, <5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "dpr_dc_ch0", "dpr_dc_ch1", "dpr_dc_ch2", "ctx_ld",
+ "dtg_prg1";
+ interrupt-parent = <&irqsteer_dcss>;
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+ <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+ clock-names = "apb", "axi", "rtrm", "pixel", "dtrc";
+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
+ <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
+ <&clk IMX8MQ_CLK_DISP_APB_SRC>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS2_PLL_125M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>;
+ assigned-clock-rates = <594000000>,
+ <800000000>,
+ <125000000>,
+ <400000000>,
+ <400000000>;
+
+ disp-dev = "hdmi_disp";
- reg_usdhc2_vmmc: usdhc2_vmmc {
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_gpio_dvfs: regulator-gpio {
- compatible = "regulator-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dvfs>;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1000000>;
- regulator-name = "gpio_dvfs";
- regulator-type = "voltage";
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- states = <900000 0x1 1000000 0x0>;
- };
- };
-
- modem_reset: modem-reset {
- compatible = "gpio-reset";
- reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- reset-post-delay-ms = <40>;
- #reset-cells = <0>;
- };
-
- wm8524: wm8524 {
- compatible = "wlf,wm8524";
- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
- clock-names = "mclk";
- wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- sound-wm8524 {
- compatible = "fsl,imx-audio-wm8524";
- model = "wm8524-audio";
- audio-cpu = <&sai2>;
- audio-codec = <&wm8524>;
- audio-routing =
- "Line Out Jack", "LINEVOUTL",
- "Line Out Jack", "LINEVOUTR";
- };
-
- sound-hdmi {
- compatible = "fsl,imx-audio-cdnhdmi";
- model = "imx-audio-hdmi";
- audio-cpu = <&sai4>;
- protocol = <0>;
- };
-
- sound-spdif {
- compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
- spdif-controller = <&spdif1>;
- spdif-out;
- spdif-in;
- };
-};
-
-&clk {
- assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>;
- assigned-clock-rates = <786432000>;
-};
-
-&iomuxc {
- pinctrl-names = "default";
-
- imx8mq-evk {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
- MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
- >;
- };
-
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16
- MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
- MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
- >;
- };
-
- pinctrl_pcie1: pcie1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16
- MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
- MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
- >;
- };
-
- pinctrl_dvfs: dvfsgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
- >;
- };
-
- pinctrl_qspi: qspigrp {
- fsl,pins = <
- MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
- MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
-
- >;
- };
-
- pinctrl_typec: typecgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
- MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
- MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
- MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
- MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
- MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_sai2: sai2grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
- MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
- >;
- };
+ status = "okay";
- pinctrl_spdif1: spdif1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
- MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
- >;
- };
+ dcss_disp0: port@0 {
+ reg = <0>;
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
+ dcss_disp0_hdmi: hdmi-endpoint {
+ remote-endpoint = <&hdmi_disp>;
+ };
};
};
-};
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- fsl,magic-packet;
- status = "okay";
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&dcss_disp0>;
+ };
- mdio {
+ hdmi_drm: hdmi_drm@32c00000 {
#address-cells = <1>;
#size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
+ compatible = "fsl,imx8mq-hdmi";
+ reg = <0x0 0x32c00000 0x0 0x33800>, /* HDP registers */
+ <0x0 0x32e40000 0x0 0x40000>; /* HDP SEC register */
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&disp_pd>;
+ port@0 {
reg = <0>;
- at803x,led-act-blind-workaround;
- at803x,eee-disabled;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic: pfuze100@08 {
- compatible = "fsl,pfuze100";
- reg = <0x08>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- sw3a_reg: sw3ab {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- regulator-always-on;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
+ hdmi_disp: endpoint {
+ remote-endpoint = <&dcss_disp0_hdmi>;
};
};
};
-
- adv7535: adv7535@3d {
- compatible = "adi,adv7535";
- reg = <0x3d>; /* PD pin is low */
- /* TODO: pin config & irq */
- video-mode = <16>; /* 1920x1080@60HZ */
- dsi-traffic-mode = <0>;
- bpp = <24>;
- status = "okay";
- port {
- dsi_to_hdmi: endpoint {
- remote-endpoint = <&mipi_dsi_ep>;
- };
- };
- };
-
- typec_ptn5100: ptn5110@50 {
- compatible = "usb,tcpci";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_typec>;
- reg = <0x50>;
- interrupt-parent = <&gpio3>;
- interrupts = <3 8>;
- ss-sel-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
- src-pdos = <0x380190c8>;
- snk-pdos = <0x380190c8 0x3802d0c8>;
- max-snk-mv = <9000>;
- max-snk-ma = <1000>;
- op-snk-mw = <9000>;
- port-type = "drp";
- default-role = "sink";
- };
};
-&hdmi {
- disp-dev = "hdmi_disp";
- status = "okay";
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "disabled";
-};
-
-&pcie0{
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>;
- disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>;
- reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&pcie1{
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie1>;
- clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
- disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>;
- reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&uart1 { /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+&hdmi_cec {
status = "okay";
};
&dcss {
- disp-dev = "hdmi_disp";
- status = "okay";
-};
-
-&lcdif {
status = "disabled";
- disp-dev = "mipi_dsi_northwest";
- display = <&display0>;
-
- display0: display@0 {
- bits-per-pixel = <24>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <9200000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <8>;
- hback-porch = <4>;
- hsync-len = <41>;
- vback-porch = <2>;
- vfront-porch = <4>;
- vsync-len = <10>;
-
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
};
-&qspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi>;
- status = "okay";
-
- flash0: n25q256a@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a";
- spi-max-frequency = <29000000>;
- spi-nor,ddr-quad-read-dummy = <6>;
- };
-};
-
-&mipi_dsi {
- reset = <&src>;
- mux-sel = <&gpr>; /* lcdif or dcss */
+&hdmi {
status = "disabled";
- port {
- mipi_dsi_ep: endpoint {
- remote-endpoint = <&dsi_to_hdmi>;
- };
- };
-};
-
-&uart3 { /* BT */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
- fsl,uart-has-rtscts;
- resets = <&modem_reset>;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- bus-width = <4>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- status = "okay";
- extcon = <&typec_ptn5100>;
- dr_mode = "otg";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&usb_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&sai2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai2>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
- <&clk IMX8MQ_CLK_SAI2_DIV>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
- status = "okay";
-};
-
-&sai4 {
- assigned-clocks = <&clk IMX8MQ_CLK_SAI4_SRC>,
- <&clk IMX8MQ_CLK_SAI4_DIV>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
- status = "okay";
-};
-
-&spdif1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spdif1>;
- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1_SRC>,
- <&clk IMX8MQ_CLK_SPDIF1_DIV>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
- status = "okay";
-};
-
-&gpu_pd {
- power-supply = <&sw1a_reg>;
-};
-
-&vpu_pd {
- power-supply = <&sw1c_reg>;
-};
-
-&gpu {
- status = "okay";
-};
-
-&vpu {
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&mu {
- status = "okay";
-};
-
-&rpmsg{
- /*
- * 64K for one rpmsg instance:
- * --0xb8000000~0xb800ffff: pingpong
- */
- vdev-nums = <1>;
- reg = <0x0 0xb8000000 0x0 0x10000>;
- status = "okay";
-};
-
-&A53_0 {
- operating-points = <
- /* kHz uV */
- 1500000 1000000
- 1300000 1000000
- 1000000 900000
- 800000 900000
- >;
- dc-supply = <®_gpio_dvfs>;
};
projects / linux.git / commitdiff