MLK-15120 ARM: imx7d: clk: select uart3 clock parent and set rate

The clock driver may enable uart clock tree when earlycon/earlyprintk
kernel param is enabled, and the clock gate specify CLK_SET_RATE_GATE,
then .of_clk_set_defaults() set the dts node assigned-rate will be failed.
So set parent and set rate in clock driver is reasonable.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 90b90b8..ccc2119 100644 (file)
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -941,6 +941,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        /* set parent of SIM1 root clock */
        imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]);
 
+       imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
+       imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000);
        imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
        imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000);
        imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);