MLK-16052-1 arm64: imx8qm: refine pcie power on imx8qm
authorRichard Zhu <hongxing.zhu@nxp.com>
Mon, 24 Jul 2017 03:20:09 +0000 (11:20 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 20:36:09 +0000 (15:36 -0500)
- Refine the pd definitions of the imx8qm/qxp hsio.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi

index f0a14a9..54b05e1 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <0>;
 
-                       pd_pcie0: PD_HSIO_PCIE_A {
-                               reg = <SC_R_PCIE_A>;
-                               #power-domain-cells = <0>;
-                               power-domains =<&pd_hsio>;
-                       };
-                       pd_pcie1: PD_HSIO_PCIE_B {
-                               reg = <SC_R_PCIE_B>;
+                       pd_serdes0: PD_HSIO_SERDES_0 {
+                               reg = <SC_R_SERDES_0>;
                                #power-domain-cells = <0>;
                                power-domains =<&pd_hsio>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               pd_pcie0: PD_HSIO_PCIE_A {
+                                       reg = <SC_R_PCIE_A>;
+                                       #power-domain-cells = <0>;
+                                       power-domains =<&pd_serdes0>;
+                               };
+                               pd_pcie1: PD_HSIO_PCIE_B {
+                                       reg = <SC_R_PCIE_B>;
+                                       #power-domain-cells = <0>;
+                                       power-domains =<&pd_serdes0>;
+                               };
                        };
-                       pd_sata0: PD_HSIO_SATA0 {
-                               reg = <SC_R_SATA_0>;
+                       pd_serdes1: PD_HSIO_SERDES_1 {
+                               reg = <SC_R_SERDES_1>;
                                #power-domain-cells = <0>;
                                power-domains =<&pd_hsio>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               pd_sata0: PD_HSIO_SATA0 {
+                                       reg = <SC_R_SATA_0>;
+                                       #power-domain-cells = <0>;
+                                       power-domains =<&pd_serdes1>;
+                               };
                        };
                        pd_gpio: PD_HSIO_GPIO {
                                reg = <SC_R_HSIO_GPIO>;
index 210cd7e..65a5254 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <0>;
 
-                       pd_pcie: PD_HSIO_PCIE_B {
-                               reg = <SC_R_PCIE_B>;
+                       pd_serdes1: PD_HSIO_SERDES_1 {
+                               reg = <SC_R_SERDES_1>;
                                #power-domain-cells = <0>;
                                power-domains =<&pd_hsio>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               pd_pcie: PD_HSIO_PCIE_B {
+                                       reg = <SC_R_PCIE_B>;
+                                       #power-domain-cells = <0>;
+                                       power-domains =<&pd_serdes1>;
+                               };
                        };
                };