Apparently, the CLK_DUMMY implementation is not so reliable, since this
can occur when doing a clk_disable_unprepare on a CLK_DUMMY clock:
[ 51.197744] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W
4.9.51-03878-g6c48bec #415
[ 51.206354] Hardware name: Freescale i.MX8MQ EVK (DT)
[ 51.211405] Call trace:
[ 51.213868] [<
ffff0000080884c8>] dump_backtrace+0x0/0x1a0
[ 51.219273] [<
ffff00000808867c>] show_stack+0x14/0x20
[ 51.224327] [<
ffff0000083dd91c>] dump_stack+0x94/0xb8
[ 51.229383] [<
ffff0000080df898>] __schedule_bug+0x50/0x70
[ 51.234786] [<
ffff000008c24578>] __schedule+0x4c0/0x580
[ 51.240013] [<
ffff000008c24674>] schedule+0x3c/0xa8
[ 51.244893] [<
ffff000008c24a70>] schedule_preempt_disabled+0x20/0x38
[ 51.251252] [<
ffff0000080f966c>] mutex_optimistic_spin+0x194/0x1d8
[ 51.257434] [<
ffff000008c25f28>] __mutex_lock_slowpath+0x38/0x140
[ 51.263529] [<
ffff000008c26074>] mutex_lock+0x44/0x60
[ 51.268589] [<
ffff0000084d9914>] clk_prepare_lock+0x44/0xd8
[ 51.274163] [<
ffff0000084db378>] clk_unprepare+0x20/0x40
[ 51.279478] [<
ffff00000860827c>] mxsfb_disable_axi_clk+0x24/0x30
[ 51.285485] [<
ffff0000086082d8>] mxsfb_irq_handler+0x50/0x60
[ 51.291144] [<
ffff000008102c84>] __handle_irq_event_percpu+0x9c/0x128
[ 51.297584] [<
ffff000008102d2c>] handle_irq_event_percpu+0x1c/0x58
[ 51.303762] [<
ffff000008102db0>] handle_irq_event+0x48/0x78
[ 51.309334] [<
ffff0000081066f0>] handle_fasteoi_irq+0xb8/0x1b0
[ 51.315165] [<
ffff000008101d7c>] generic_handle_irq+0x24/0x38
[ 51.320910] [<
ffff0000081023ec>] __handle_domain_irq+0x5c/0xb8
[ 51.326742] [<
ffff00000808163c>] gic_handle_irq+0xbc/0x168
[ 51.332226] Exception stack(0xffff000009253d90 to 0xffff000009253ec0)
Since AXI and DISP_AXI are optional clocks according to the driver,
there is no need for dummy clocks in DTS, so remove them.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
lcdif: lcdif@30320000 {
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
reg = <0x0 0x30320000 0x0 0x10000>;
- clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
- <&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "pix", "axi", "disp_axi";
+ clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>;
+ clock-names = "pix";
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rate = <594000000>;