Use drm debug log function.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
******************************************************************************
*/
+#include <drm/drmP.h>
#include <linux/io.h>
#include "API_AFE_ss28fdsoi_kiran_hdmitx.h"
#include "ss28fdsoi_hdmitx_table.h"
charge_pump_gain.msb = 8;
charge_pump_gain.lsb = 0;
- pr_info
+ DRM_INFO
("phy_cfg_hdp() num_lanes: %0d, vicMode: %0d, color depth: %0d-bit, encoding: %0d\n",
num_lanes, vicMode, bpp, format);
/* Check if row was found */
ftemp = pixel_freq_khz;
if (row + 1) {
- pr_info
+ DRM_INFO
("Pixel clock frequency (%u kHz) is supported in this color depth (%0d-bit). Settings found in row %0d\n",
ftemp, bpp, row);
} else {
- pr_info
+ DRM_INFO
("Pixel clock frequency (%u kHz) not supported for this color depth (%0d-bit), row=%d\n",
ftemp, bpp, row);
}
pixel_freq_khz * character_clock_ratio_num /
character_clock_ratio_den;
ftemp = character_freq_khz;
- pr_info("Character clock frequency: %u kHz.\n", ftemp);
+ DRM_INFO("Character clock frequency: %u kHz.\n", ftemp);
/* Extract particular values from the ss28fdsoi_hdmitx_clock_control_table table */
set_field_value(&cmnda_pll0_hs_sym_div_sel,
[PLL_FB_DIV_TOTAL]);
/* Display parameters (informative message) */
- pr_info("set_field_value() cmnda_pll0_hs_sym_div_sel : 0x%X\n",
+ DRM_DEBUG("set_field_value() cmnda_pll0_hs_sym_div_sel : 0x%X\n",
cmnda_pll0_hs_sym_div_sel.value);
- pr_info("set_field_value() cmnda_pll0_ip_div : 0x%02X\n",
+ DRM_DEBUG("set_field_value() cmnda_pll0_ip_div : 0x%02X\n",
cmnda_pll0_ip_div.value);
- pr_info("set_field_value() cmnda_pll0_fb_div_low : 0x%03X\n",
+ DRM_DEBUG("set_field_value() cmnda_pll0_fb_div_low : 0x%03X\n",
cmnda_pll0_fb_div_low.value);
- pr_info("set_field_value() cmnda_pll0_fb_div_high : 0x%03X\n",
+ DRM_DEBUG("set_field_value() cmnda_pll0_fb_div_high : 0x%03X\n",
cmnda_pll0_fb_div_high.value);
- pr_info("set_field_value() cmn_ref_clk_dig_div : 0x%X\n",
+ DRM_DEBUG("set_field_value() cmn_ref_clk_dig_div : 0x%X\n",
cmn_ref_clk_dig_div.value);
- pr_info("set_field_value() divider_scaler : 0x%X\n",
+ DRM_DEBUG("set_field_value() divider_scaler : 0x%X\n",
divider_scaler.value);
- pr_info("set_field_value() cmnda_hs_clk_0_sel : %0d\n",
+ DRM_DEBUG("set_field_value() cmnda_hs_clk_0_sel : %0d\n",
cmnda_hs_clk_0_sel.value);
- pr_info("set_field_value() cmnda_hs_clk_1_sel : %0d\n",
+ DRM_DEBUG("set_field_value() cmnda_hs_clk_1_sel : %0d\n",
cmnda_hs_clk_1_sel.value);
- pr_info("set_field_value() tx_subrate : %0d\n",
+ DRM_DEBUG("set_field_value() tx_subrate : %0d\n",
tx_subrate.value);
- pr_info("set_field_value() vco_ring_select : %0d\n",
+ DRM_DEBUG("set_field_value() vco_ring_select : %0d\n",
vco_ring_select.value);
- pr_info("set_field_value() pll_feedback_divider_total: %0d\n",
+ DRM_DEBUG("set_field_value() pll_feedback_divider_total: %0d\n",
pll_feedback_divider_total.value);
vco_freq_khz =
pll_feedback_divider_total.value);
ftemp = vco_freq_khz;
if (row + 1) {
- pr_info
+ DRM_INFO
("VCO frequency (%u kHz) is supported. Settings found in row %0d\n",
ftemp, row);
} else {
- pr_info("VCO frequency (%u kHz) not supported\n", ftemp);
+ DRM_INFO("VCO frequency (%u kHz) not supported\n", ftemp);
}
/* Extract particular values from the ss28fdsoi_hdmitx_pll_tuning_table table */
[CHARGE_PUMP_GAIN]);
/* Display parameters (informative message) */
- pr_info("set_field_value() voltage_to_current_coarse : 0x%X\n",
+ DRM_DEBUG("set_field_value() voltage_to_current_coarse : 0x%X\n",
voltage_to_current_coarse.value);
- pr_info("set_field_value() voltage_to_current : 0x%X\n",
+ DRM_DEBUG("set_field_value() voltage_to_current : 0x%X\n",
voltage_to_current.value);
- pr_info("set_field_value() ndac_ctrl : 0x%X\n",
+ DRM_DEBUG("set_field_value() ndac_ctrl : 0x%X\n",
ndac_ctrl.value);
- pr_info("set_field_value() pmos_ctrl : 0x%02X\n",
+ DRM_DEBUG("set_field_value() pmos_ctrl : 0x%02X\n",
pmos_ctrl.value);
- pr_info("set_field_value() ptat_ndac_ctrl : 0x%02X\n",
+ DRM_DEBUG("set_field_value() ptat_ndac_ctrl : 0x%02X\n",
ptat_ndac_ctrl.value);
- pr_info("set_field_value() charge_pump_gain : 0x%03X\n",
+ DRM_DEBUG("set_field_value() charge_pump_gain : 0x%03X\n",
charge_pump_gain.value);
/* ---------------------------------------------------------------
static void arc_power_up(state_struct *state)
{
- pr_info("arc_power_up()\n");
+ DRM_DEBUG("arc_power_up()\n");
/* register CMN_RXCAL_OVRD */
Afe_write(state, 0x5025, 0x0001);
uint16_t new_calib_code;
uint16_t rdata;
- pr_info("aux_cal_cfg() ARC programming\n");
+ DRM_DEBUG("aux_cal_cfg() ARC programming\n");
/* register TX_DIG_CTRL_REG_2 */
prev_calib_code = Afe_read(state, 0x5024);
/* register CMN_TXPUCAL_CTRL */
static void arc_config(state_struct *state)
{
- pr_info("arc_config() ARC programming\n");
+ DRM_DEBUG("arc_config() ARC programming\n");
/* register TX_ANA_CTRL_REG_2 */
Afe_write(state, 0x5021, 0x0100);
while (!(Afe_read(state, 0xC008) & (1 << 6))) ;
#ifdef __ARC_CONFIG__
- arc_power_up();
- arc_calibrate();
- arc_config();
+ arc_power_up(state);
+ arc_calibrate(state);
+ arc_config(state);
#endif
/* PHY_DP_MODE_CTL */
******************************************************************************
*/
+#include <drm/drmP.h>
#include "API_AFE_t28hpc_hdmitx.h"
static char inside(u32 value, u32 left_sharp_corner,
cmnda_pll0_fb_div_high.value = 0x00A;
ftemp = pixel_freq_khz;
- pr_info(" VIC %d, pixel clock %u kHz\n", vicMode, ftemp);
+ DRM_INFO(" VIC %d, pixel clock %u kHz\n", vicMode, ftemp);
/* Set field position */
cmnda_pll0_hs_sym_div_sel.msb = 9;
character_clock_ratio_den = 1;
break;
default:
- pr_warn("Invalid ColorDepth\n");
+ DRM_WARN("Invalid ColorDepth\n");
}
break;
character_clock_ratio_num / character_clock_ratio_den;
ftemp = pixel_freq_khz;
ftemp2 = character_freq_khz;
- pr_info
+ DRM_INFO
("Pixel clock frequency: %u kHz, character clock frequency: %u, color depth is %0d-bit.\n",
ftemp, ftemp2, bpp);
if (pixel_clk_from_phy == 0) {
400);
} else {
ftemp = pixel_freq_khz;
- pr_warn
+ DRM_WARN
("Pixel clock frequency (%u) is outside of the supported range\n",
ftemp);
}
400);
} else {
ftemp = pixel_freq_khz;
- pr_info
+ DRM_ERROR
("Pixel clock frequency (%u) is outside of the supported range\n",
ftemp);
}
360);
} else {
ftemp = pixel_freq_khz;
- pr_info
+ DRM_ERROR
("Pixel clock frequency (%u) is outside of the supported range\n",
ftemp);
}
400);
} else {
ftemp = pixel_freq_khz;
- pr_info
+ DRM_ERROR
("Pixel clock frequency (%u) is outside of the supported range\n",
ftemp);
}
case CLK_RATIO_1_2:
if (!(inside(pixel_freq_khz, 594000, 594000))) {
ftemp = pixel_freq_khz;
- pr_info
+ DRM_ERROR
("Pixel clock frequency (%u) is outside of the supported range\n",
ftemp);
} else {
case CLK_RATIO_5_8:
if (!(inside(pixel_freq_khz, 594000, 594000))) {
ftemp = pixel_freq_khz;
- pr_info
+ DRM_ERROR
("Pixel clock frequency (%u) is outside of the supported range\n",
ftemp);
} else {
case CLK_RATIO_3_4:
if (!(inside(pixel_freq_khz, 594000, 594000))) {
ftemp = pixel_freq_khz;
- pr_info
+ DRM_ERROR
("Pixel clock frequency (%u) is outside of the supported range\n",
ftemp);
} else {
pixel_freq_khz * pll_feedback_divider_total.value /
cmnda_pll0_ip_div.value;
ftemp = vco_freq;
- pr_info("VCO frequency is %u kHz\n", ftemp);
+ DRM_INFO("VCO frequency is %u kHz\n", ftemp);
if (inside(vco_freq, 1700000, 2000000)) {
set_field_value(&voltage_to_current_coarse, 0x04);
set_field_value(&charge_pump_gain, 0xA2);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
set_field_value(&charge_pump_gain, 0x84);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
set_field_value(&charge_pump_gain, 0x81);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
set_field_value(&charge_pump_gain, 0x46);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
set_field_value(&charge_pump_gain, 0x85);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
set_field_value(&charge_pump_gain, 0x82);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
set_field_value(&charge_pump_gain, 0x4A);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
set_field_value(&charge_pump_gain, 0x45);
break;
default:
- pr_warn
+ DRM_WARN
("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
pll_feedback_divider_total.value, ftemp);
}
} else
- pr_warn
+ DRM_WARN
("VCO frequency %u kHz is outside of the supported range\n",
ftemp);
break;
default:
ftemp = pixel_freq_khz;
- pr_warn
+ DRM_WARN
("This pixel clock frequency (%u kHz) is not supported with this (%0d-bit) color depth.\n",
ftemp, bpp);
}
0x00);
break;
default:
- pr_warn
+ DRM_WARN
("This pixel clock frequency (%d KHz) is not supported with this (%0d-bit) color depth.\n",
pixel_freq_khz, bpp);
}
} else {
ftemp = pixel_freq_khz;
- pr_warn
+ DRM_WARN
("This pixel clock frequency (%u kHz) is not supported.\n",
ftemp);
}
refclk_freq_khz * pll_feedback_divider_total.value /
cmnda_pll0_ip_div.value;
ftemp = vco_freq;
- pr_info("VCO frequency is %u kHz\n", ftemp);
+ DRM_INFO("VCO frequency is %u kHz\n", ftemp);
if (inside(vco_freq, 1980000, 1980000)) {
set_field_value(&voltage_to_current_coarse, 0x04);
set_field_value(&vco_cal_code, 292);
} else {
ftemp = vco_freq;
- pr_warn("Current vco_freq (%u kHz) is not supported.\n",
+ DRM_WARN("Current vco_freq (%u kHz) is not supported.\n",
ftemp);
}
static void arc_power_up(state_struct *state)
{
- pr_info("arc_power_up()\n");
+ DRM_DEBUG("arc_power_up()\n");
/* register CMN_RXCAL_OVRD */
Afe_write(state, 0x5025, 0x0001);
uint16_t new_calib_code;
uint16_t rdata;
- pr_info("aux_cal_cfg() ARC programming\n");
+ DRM_DEBUG("aux_cal_cfg() ARC programming\n");
/* register TX_DIG_CTRL_REG_2 */
prev_calib_code = Afe_read(state, 0x5024);
/* register CMN_TXPUCAL_CTRL */
static void arc_config(state_struct *state)
{
- pr_info("arc_config() ARC programming\n");
+ DRM_DEBUG("arc_config() ARC programming\n");
/* register TX_ANA_CTRL_REG_2 */
Afe_write(state, 0x5021, 0x0100);
#ifdef DEBUG_FW_LOAD
void dp_fw_load(state_struct *state)
{
- pr_info("loading hdmi firmware\n");
+ DRM_INFO("loading hdmi firmware\n");
CDN_API_LoadFirmware(state,
(u8 *)mhdp_iram0_get_ptr(),
mhdp_iram0_get_size(),
pr_info("CDN_API_SetClock completed\n");
cdn_apb_write(state, APB_CTRL << 2, 0);
- pr_info("Started firmware!\n");
+ DRM_INFO("Started firmware!\n");
ret = CDN_API_CheckAlive_blocking(state);
if (ret != 0) {
- pr_err("CDN_API_CheckAlive failed - check firmware!\n");
+ DRM_ERROR("CDN_API_CheckAlive failed - check firmware!\n");
return -ENXIO;
} else
- pr_info("CDN_API_CheckAlive returned ret = %d\n", ret);
+ DRM_INFO("CDN_API_CheckAlive returned ret = %d\n", ret);
/* turn on IP activity */
ret = CDN_API_MainControl_blocking(state, 1, &resp);
- pr_info("CDN_API_MainControl_blocking (ret = %d resp = %u)\n",
+ DRM_INFO("CDN_API_MainControl_blocking (ret = %d resp = %u)\n",
ret, resp);
ret = CDN_API_General_Test_Echo_Ext_blocking(state, echo_msg, echo_resp,
sizeof(echo_msg), CDN_BUS_TYPE_APB);
if (0 != strncmp(echo_msg, echo_resp, sizeof(echo_msg))) {
- pr_err("CDN_API_General_Test_Echo_Ext_blocking - echo test failed, check firmware!");
+ DRM_ERROR("CDN_API_General_Test_Echo_Ext_blocking - echo test failed, check firmware!");
return -ENXIO;
}
- pr_info("CDN_API_General_Test_Echo_Ext_blocking (ret = %d echo_resp = %s)\n",
+ DRM_INFO("CDN_API_General_Test_Echo_Ext_blocking (ret = %d echo_resp = %s)\n",
ret, echo_resp);
/* Line swaping */
CDN_API_General_Write_Register_blocking(state,
ADDR_SOURCD_PHY + (LANES_CONFIG << 2), 0x0040001b);
- pr_info("CDN_API_General_Write_Register_blockin ... setting LANES_CONFIG\n");
+ DRM_INFO("CDN_API_General_Write_Register_blockin ... setting LANES_CONFIG\n");
return 0;
}
/* PHY initialization while phy reset pin is active */
AFE_init(state, num_lanes, (ENUM_AFE_LINK_RATE)max_link_rate);
- pr_info("AFE_init\n");
+ DRM_INFO("AFE_init\n");
/* In this point the phy reset should be deactivated */
imx_hdp_call(hdp, phy_reset, hdp->ipcHndl, 1);
- pr_info("deasserted reset\n");
+ DRM_INFO("deasserted reset\n");
/* PHY power set */
AFE_power(state, num_lanes, (ENUM_AFE_LINK_RATE)max_link_rate);
- pr_info("AFE_power exit\n");
+ DRM_INFO("AFE_power exit\n");
/* Video off */
ret = CDN_API_DPTX_SetVideo_blocking(state, 0);
- pr_info("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
+ DRM_INFO("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
return true;
}
lane_mapping,
ext_host_cap
);
- pr_info("CDN_API_DPTX_SetHostCap_blocking (ret = %d)\n", ret);
+ DRM_INFO("CDN_API_DPTX_SetHostCap_blocking (ret = %d)\n", ret);
switch (max_link_rate) {
case 0x0a:
bt_type,
transfer_unit
);
- pr_info("CDN_API_DPTX_Set_VIC_blocking (ret = %d)\n", ret);
+ DRM_INFO("CDN_API_DPTX_Set_VIC_blocking (ret = %d)\n", ret);
ret = CDN_API_DPTX_TrainingControl_blocking(state, 1);
- pr_info("CDN_API_DPTX_TrainingControl_blocking (ret = %d)\n", ret);
+ DRM_INFO("CDN_API_DPTX_TrainingControl_blocking (ret = %d)\n", ret);
/* Set video on */
ret = CDN_API_DPTX_SetVideo_blocking(state, 1);
- pr_info("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
+ DRM_INFO("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
udelay(1000);
}
ret = CDN_API_DPTX_Read_EDID_blocking(state, 1, 1, &edidResp);
break;
default:
- pr_warn("EDID block %x read not support\n", block);
+ DRM_WARN("EDID block %x read not support\n", block);
}
memcpy(buf, edidResp.buff, 128);
#ifdef DEBUG_FW_LOAD
void hdmi_fw_load(state_struct *state)
{
- pr_info("loading hdmi firmware\n");
+ DRM_INFO("loading hdmi firmware\n");
CDN_API_LoadFirmware(state,
(u8 *)hdmitx_iram0_get_ptr(),
hdmitx_iram0_get_size(),
/* moved from CDN_API_LoadFirmware */
cdn_apb_write(state, APB_CTRL << 2, 0);
- pr_info("Started firmware!\n");
+ DRM_INFO("Started firmware!\n");
ret = CDN_API_CheckAlive_blocking(state);
if (ret != 0) {
- pr_err("CDN_API_CheckAlive failed - check firmware!\n");
+ DRM_ERROR("CDN_API_CheckAlive failed - check firmware!\n");
return -ENXIO;
} else
- pr_info("CDN_API_CheckAlive returned ret = %d\n", ret);
+ DRM_INFO("CDN_API_CheckAlive returned ret = %d\n", ret);
/* turn on IP activity */
ret = CDN_API_MainControl_blocking(state, 1, &sts);
- pr_info("CDN_API_MainControl_blocking ret = %d sts = %u\n", ret, sts);
+ DRM_INFO("CDN_API_MainControl_blocking ret = %d sts = %u\n", ret, sts);
ret = CDN_API_General_Test_Echo_Ext_blocking(state, echo_msg, echo_resp,
sizeof(echo_msg), CDN_BUS_TYPE_APB);
if (0 != strncmp(echo_msg, echo_resp, sizeof(echo_msg))) {
- pr_err("CDN_API_General_Test_Echo_Ext_blocking - echo test failed, check firmware!");
+ DRM_ERROR("CDN_API_General_Test_Echo_Ext_blocking - echo test failed, check firmware!");
return -ENXIO;
}
- pr_info("CDN_API_General_Test_Echo_Ext_blocking - APB(ret = %d echo_resp = %s)\n",
+ DRM_INFO("CDN_API_General_Test_Echo_Ext_blocking - APB(ret = %d echo_resp = %s)\n",
ret, echo_resp);
return 0;
F_SOURCE_PHY_LANE0_SWAP(3) | F_SOURCE_PHY_LANE1_SWAP(0) |
F_SOURCE_PHY_LANE2_SWAP(1) | F_SOURCE_PHY_LANE3_SWAP(2) |
F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1));
- pr_info("CDN_API_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret);
+ DRM_INFO("CDN_API_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret);
return true;
}
ret = CDN_API_HDMITX_Init_blocking(state);
if (ret != CDN_OK) {
- pr_info("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret);
+ DRM_INFO("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret);
return;
}
/* Set HDMI TX Mode */
ret = CDN_API_HDMITX_Set_Mode_blocking(state, ptype, character_freq_khz);
if (ret != CDN_OK) {
- pr_info("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
+ DRM_INFO("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
return;
}
ret = CDN_API_Set_AVI(state, vic, format, bw_type);
if (ret != CDN_OK) {
- pr_info("CDN_API_Set_AVI ret = %d\n", ret);
+ DRM_INFO("CDN_API_Set_AVI ret = %d\n", ret);
return;
}
ret = CDN_API_HDMITX_SetVic_blocking(state, vic, color_depth, format);
if (ret != CDN_OK) {
- pr_info("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
+ DRM_INFO("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
return;
}
ret = CDN_API_CheckAlive_blocking(state);
if (ret != 0) {
- pr_err("NO HDMI FW running\n");
+ DRM_ERROR("NO HDMI FW running\n");
return -ENXIO;
}
sizeof(echo_msg),
CDN_BUS_TYPE_APB);
if (ret != 0) {
- pr_err("HDMI mailbox access failed\n");
+ DRM_ERROR("HDMI mailbox access failed\n");
return -ENXIO;
}
F_SOURCE_PHY_LANE3_SWAP(3) |
F_SOURCE_PHY_COMB_BYPASS(0)
| F_SOURCE_PHY_20_10(1));
- pr_info
+ DRM_INFO
("CDN_API_General_Write_Register_blocking LANES_CONFIG ret = %d\n",
ret);
ret = CDN_API_HDMITX_Init_blocking(state);
if (ret != CDN_OK) {
- pr_info("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret);
+ DRM_ERROR("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret);
return;
}
/* Set HDMI TX Mode */
ret = CDN_API_HDMITX_Set_Mode_blocking(state, ptype, character_freq_khz);
if (ret != CDN_OK) {
- pr_info("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
+ DRM_ERROR("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
return;
}
ret = CDN_API_Set_AVI(state, vic, format, bw_type);
if (ret != CDN_OK) {
- pr_info("CDN_API_Set_AVI ret = %d\n", ret);
+ DRM_ERROR("CDN_API_Set_AVI ret = %d\n", ret);
return;
}
ret = CDN_API_HDMITX_SetVic_blocking(state, vic, color_depth, format);
if (ret != CDN_OK) {
- pr_info("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
+ DRM_ERROR("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
return;
}
}
if (i == VIC_MODE_COUNT) {
- pr_err("vmode is wrong!\n");
+ DRM_ERROR("vmode is wrong!\n");
j = 7;
return j;
}
sciErr = sc_ipc_getMuID(&hdp->mu_id);
if (sciErr != SC_ERR_NONE) {
- pr_err("Cannot obtain MU ID\n");
+ DRM_ERROR("Cannot obtain MU ID\n");
return -EINVAL;
}
sciErr = sc_ipc_open(&hdp->ipcHndl, hdp->mu_id);
if (sciErr != SC_ERR_NONE) {
- pr_err("sc_ipc_open failed! (sciError = %d)\n", sciErr);
+ DRM_ERROR("sc_ipc_open failed! (sciError = %d)\n", sciErr);
return -EINVAL;
}
/* set the pixel link mode and pixel type */
sciErr = sc_misc_set_control(ipcHndl, SC_R_HDMI, SC_C_PHY_RESET, reset);
if (sciErr != SC_ERR_NONE)
- pr_err("SC_R_HDMI PHY reset failed %d!\n", sciErr);
+ DRM_ERROR("SC_R_HDMI PHY reset failed %d!\n", sciErr);
}
int imx8qm_clock_init(struct hdp_clks *clks)
ret = imx_hdp_call(hdp, fw_init, &hdp->state);
if (ret < 0) {
- pr_err("Failed to initialise HDP firmware\n");
DRM_ERROR("Failed to initialise HDP firmware\n");
return ret;
}
projects / linux.git / commitdiff