The HDMI digital PLL, bus clock and core clock need to change to match the
settings used by the Linux driver. This allows the SECO to start and
initialize the HDMI/DP firmware.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
(cherry picked from commit
d2713d11afc35bc2ce546f9bd065cc7477ee65cc)
static void display_set_clocks(void)
{
- const sc_pm_clock_rate_t pll = 1188000000;
- const sc_pm_clock_rate_t hdmi_core_clock = pll / 10;
- const sc_pm_clock_rate_t hdmi_bus_clock = pll / 14;
+ const sc_pm_clock_rate_t pll = 657000000;
+ const sc_pm_clock_rate_t hdmi_core_clock = pll / 5; /* 135.000 Mhz */
+ const sc_pm_clock_rate_t hdmi_bus_clock = pll / 8; /* 83.375 Mhz */
SC_PM_SET_RESOURCE_POWER_MODE(-1,
SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF);