interrupt-parent = <&gic>;
};
+ mu8: mu@5d230000 {
+ compatible = "fsl,imx-m4-mu";
+ reg = <0x0 0x5d230000 0x0 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lsio_mu8a>;
+ status = "okay";
+ };
+
mu: mu@5d1c0000 {
compatible = "fsl,imx8-mu";
reg = <0x0 0x5d1c0000 0x0 0x10000>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
+ pd_lsio_mu8a: PD_LSIO_MU8A {
+ reg = <SC_R_MU_8A>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
};
pd_conn: PD_CONN {
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
+ pd_lsio_mu8a: PD_LSIO_MU8A {
+ reg = <SC_R_MU_8A>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_mu9a: PD_LSIO_MU9A {
+ reg = <SC_R_MU_9A>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
};
pd_conn: PD_CONN {
interrupt-parent = <&gic>;
};
+ mu8: mu@5d230000 {
+ compatible = "fsl,imx-m4-mu";
+ reg = <0x0 0x5d230000 0x0 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lsio_mu8a>;
+ status = "okay";
+ };
+
+ mu9: mu@5d240000 {
+ compatible = "fsl,imx-m4-mu";
+ reg = <0x0 0x5d240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lsio_mu9a>;
+ status = "okay";
+ };
+
mu: mu@5d1c0000 {
compatible = "fsl,imx8-mu";
reg = <0x0 0x5d1c0000 0x0 0x10000>;
#define PD_LSIO_PWM_7 lsio_pwm7
#define PD_LSIO_MU5A lsio_mu5a
#define PD_LSIO_MU6A lsio_mu6a
+#define PD_LSIO_MU8A lsio_mu8a
+#define PD_LSIO_MU9A lsio_mu9a
#define PD_CONN connectivity_power_domain
#define PD_CONN_SDHC_0 conn_sdhc0