MLK-20886-7 DTS: imx8qm/qxp: Add MU8 and MU9 nodes
authorYe Li <ye.li@nxp.com>
Thu, 31 Jan 2019 06:31:02 +0000 (22:31 -0800)
committerYe Li <ye.li@nxp.com>
Fri, 24 May 2019 11:28:16 +0000 (04:28 -0700)
We use MU8 and MU9 to communicate with M4_0 and M4_1 in u-boot. Add
relevant nodes for the MU driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b06674a91991fe3bfe5a2f6000195cb8546c72a6)

arch/arm/dts/fsl-imx8dx.dtsi
arch/arm/dts/fsl-imx8qm-device.dtsi
arch/arm/dts/fsl-imx8qm.dtsi
include/dt-bindings/soc/imx8_pd.h

index 831c625..05acda8 100644 (file)
                interrupt-parent = <&gic>;
        };
 
+       mu8: mu@5d230000 {
+               compatible = "fsl,imx-m4-mu";
+               reg = <0x0 0x5d230000 0x0 0x10000>;
+               interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&pd_lsio_mu8a>;
+               status = "okay";
+       };
+
        mu: mu@5d1c0000 {
                compatible = "fsl,imx8-mu";
                reg = <0x0 0x5d1c0000 0x0 0x10000>;
                                #power-domain-cells = <0>;
                                power-domains = <&pd_lsio>;
                        };
+                       pd_lsio_mu8a: PD_LSIO_MU8A {
+                               reg = <SC_R_MU_8A>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_lsio>;
+                       };
                };
 
                pd_conn: PD_CONN {
index 20a84bf..d9bc9c6 100644 (file)
                                #power-domain-cells = <0>;
                                power-domains = <&pd_lsio>;
                        };
+                       pd_lsio_mu8a: PD_LSIO_MU8A {
+                               reg = <SC_R_MU_8A>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_lsio>;
+                       };
+                       pd_lsio_mu9a: PD_LSIO_MU9A {
+                               reg = <SC_R_MU_9A>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_lsio>;
+                       };
                };
 
                pd_conn: PD_CONN {
index cc076c2..8f0b047 100644 (file)
                interrupt-parent = <&gic>;
        };
 
+       mu8: mu@5d230000 {
+               compatible = "fsl,imx-m4-mu";
+               reg = <0x0 0x5d230000 0x0 0x10000>;
+               interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&pd_lsio_mu8a>;
+               status = "okay";
+       };
+
+       mu9: mu@5d240000 {
+               compatible = "fsl,imx-m4-mu";
+               reg = <0x0 0x5d240000 0x0 0x10000>;
+               interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&pd_lsio_mu9a>;
+               status = "okay";
+       };
+
        mu: mu@5d1c0000 {
                compatible = "fsl,imx8-mu";
                reg = <0x0 0x5d1c0000 0x0 0x10000>;
index 6411c99..966d971 100644 (file)
@@ -95,6 +95,8 @@
 #define PD_LSIO_PWM_7               lsio_pwm7
 #define PD_LSIO_MU5A                lsio_mu5a
 #define PD_LSIO_MU6A                lsio_mu6a
+#define PD_LSIO_MU8A                lsio_mu8a
+#define PD_LSIO_MU9A                lsio_mu9a
 
 #define PD_CONN                     connectivity_power_domain
 #define PD_CONN_SDHC_0              conn_sdhc0