MLK-13869 ARM: dts: imx7: route interrupts through GPC

We need to "logically" route interrupts through GPC instead of directly
through GIC in order to support low power mode with SCU and L2 off.

Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>

diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 071ebaf..b06eeda 100644 (file)
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -251,42 +251,12 @@
                compatible = "fsl,imx6q-caam-snvs";
                reg = <0x30370000 0x10000>;
        };
-
-       gpc: gpc@303a0000 {
-               compatible = "fsl,imx7d-gpc";
-               reg = <0x303a0000 0x10000>;
-               interrupt-controller;
-               interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-               #interrupt-cells = <3>;
-               interrupt-parent = <&intc>;
-               fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>;
-               mipi-phy-supply = <&reg_1p0d>;
-               pcie-phy-supply = <&reg_1p0d>;
-               vcc-supply = <&reg_1p2>;
-       };
-
        iomuxc_lpsr_gpr: lpsr-gpr@30270000 {
                compatible = "fsl,imx7d-lpsr-gpr";
                reg = <0x30270000 0x10000>;
        };
 };
 
-&anatop {
-       reg_1p2: regulator-vdd1p2@220 {
-               compatible = "fsl,anatop-regulator";
-               regulator-name = "vdd1p2";
-               regulator-min-microvolt = <1100000>;
-               regulator-max-microvolt = <1300000>;
-               anatop-reg-offset = <0x220>;
-               anatop-vol-bit-shift = <8>;
-               anatop-vol-bit-width = <5>;
-               anatop-min-bit-val = <8>;
-               anatop-min-voltage = <1100000>;
-               anatop-max-voltage = <1300000>;
-               anatop-enable-bit = <31>;
-       };
-};
-
 &aips2 {
        flextimer1: flextimer@30640000 {
                compatible = "fsl,imx7d-flextimer";

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 73acca1..63720ab 100644 (file)
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -110,7 +110,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-               interrupt-parent = <&intc>;
+               interrupt-parent = <&gpc>;
                ranges;
 
                funnel@30041000 {
@@ -296,14 +296,18 @@
                              <0x31002000 0x2000>,
                              <0x31004000 0x2000>,
                              <0x31006000 0x2000>;
+                       interrupt-parent = <&intc>;
                };
 
                timer {
                        compatible = "arm,armv7-timer";
+                       arm,cpu-registers-not-fw-configured;
                        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                                     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                                     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                                     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                       interrupt-parent = <&intc>;
+                       clock-frequency = <8000000>;
                };
 
                aips1: aips-bus@30000000 {
@@ -313,6 +317,19 @@
                        reg = <0x30000000 0x400000>;
                        ranges;
 
+                       gpc: gpc@303a0000 {
+                               compatible = "fsl,imx7d-gpc";
+                               reg = <0x303a0000 0x10000>;
+                               interrupt-controller;
+                               interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                               #interrupt-cells = <3>;
+                               interrupt-parent = <&intc>;
+                               fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>;
+                               mipi-phy-supply = <&reg_1p0d>;
+                               pcie-phy-supply = <&reg_1p0d>;
+                               vcc-supply = <&reg_1p2>;
+                       };
+
                        gpio1: gpio@30200000 {
                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
                                reg = <0x30200000 0x10000>;
@@ -510,6 +527,21 @@
                                        anatop-max-voltage = <1200000>;
                                        anatop-enable-bit = <0>;
                                };
+
+                               reg_1p2: regulator-vdd1p2@220 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd1p2";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        anatop-reg-offset = <0x220>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <8>;
+                                        anatop-min-voltage = <1100000>;
+                                        anatop-max-voltage = <1300000>;
+                                        anatop-enable-bit = <31>;
+                               };
+
                        };
 
                        snvs: snvs@30370000 {