fsl,max_ddr_freq = <528000000>;
};
- ocram: sram@00905000 {
+ ocram: sram@905000 {
compatible = "mmio-sram";
- reg = <0x00905000 0x3B000>;
+ reg = <0x905000 0x3B000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- ocram_optee: sram@00938000 {
+ ocram_optee: sram@938000 {
compatible = "fsl,optee-lpm-sram";
- reg = <0x00938000 0x8000>;
- overw_reg = <&ocram 0x00905000 0x33000>;
+ reg = <0x938000 0x8000>;
+ overw_reg = <&ocram 0x905000 0x33000>;
};
bus@2000000 { /* AIPS1 */
fsl,max_ddr_freq = <400000000>;
};
- ocrams: sram@00900000 {
+ ocrams: sram@900000 {
compatible = "fsl,lpm-sram";
- reg = <0x00900000 0x4000>;
+ reg = <0x900000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
- ocrams_ddr: sram@00904000 {
+ ocrams_ddr: sram@904000 {
compatible = "fsl,ddr-lpm-sram";
- reg = <0x00904000 0x1000>;
+ reg = <0x904000 0x1000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
- ocram: sram@00905000 {
+ ocram: sram@905000 {
compatible = "mmio-sram";
- reg = <0x00905000 0x1B000>;
+ reg = <0x905000 0x1B000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
- ocram_optee: sram@00918000 {
+ ocram_optee: sram@918000 {
compatible = "fsl,optee-lpm-sram";
- reg = <0x00918000 0x8000>;
- overw_reg = <&ocram 0x00905000 0x13000>;
+ reg = <0x918000 0x8000>;
+ overw_reg = <&ocram 0x905000 0x13000>;
};
intc: interrupt-controller@a01000 {
fsl,max_ddr_freq = <400000000>;
};
- ocrams: sram@00900000 {
+ ocrams: sram@900000 {
compatible = "fsl,lpm-sram";
- reg = <0x00900000 0x4000>;
+ reg = <0x900000 0x4000>;
};
- ocrams_ddr: sram@00904000 {
+ ocrams_ddr: sram@904000 {
compatible = "fsl,ddr-lpm-sram";
- reg = <0x00904000 0x1000>;
+ reg = <0x904000 0x1000>;
};
- ocram: sram@00905000 {
+ ocram: sram@905000 {
compatible = "mmio-sram";
- reg = <0x00905000 0x1B000>;
+ reg = <0x905000 0x1B000>;
};
- ocram_optee: sram@00918000 {
+ ocram_optee: sram@918000 {
compatible = "fsl,optee-lpm-sram";
- reg = <0x00918000 0x8000>;
- overw_reg = <&ocram 0x00905000 0x13000>;
+ reg = <0x918000 0x8000>;
+ overw_reg = <&ocram 0x905000 0x13000>;
};
intc: interrupt-controller@a01000 {
fsl,max_ddr_freq = <400000000>;
};
- ocrams: sram@008f8000 {
+ ocrams: sram@8f8000 {
compatible = "fsl,lpm-sram";
- reg = <0x008f8000 0x4000>;
+ reg = <0x8f8000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCRAM_S>;
};
- ocrams_ddr: sram@00900000 {
+ ocrams_ddr: sram@900000 {
compatible = "fsl,ddr-lpm-sram";
- reg = <0x00900000 0x1000>;
+ reg = <0x900000 0x1000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
- ocram: sram@00901000 {
+ ocram: sram@901000 {
compatible = "mmio-sram";
- reg = <0x00901000 0x1F000>;
+ reg = <0x901000 0x1F000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
- ocram_mf: sram-mf@00900000 {
+ ocram_mf: sram-mf@900000 {
compatible = "fsl,mega-fast-sram";
- reg = <0x00900000 0x20000>;
+ reg = <0x900000 0x20000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
fsl,max_ddr_freq = <400000000>;
};
- ocrams: sram@00900000 {
+ ocrams: sram@900000 {
compatible = "fsl,lpm-sram";
- reg = <0x00900000 0x4000>;
+ reg = <0x900000 0x4000>;
};
- ocrams_ddr: sram@00904000 {
+ ocrams_ddr: sram@904000 {
compatible = "fsl,ddr-lpm-sram";
- reg = <0x00904000 0x1000>;
+ reg = <0x904000 0x1000>;
};
- ocram: sram@00905000 {
+ ocram: sram@905000 {
compatible = "mmio-sram";
reg = <0x00905000 0x1B000>;
};
- ocram_optee: sram@00918000 {
+ ocram_optee: sram@918000 {
compatible = "fsl,optee-lpm-sram";
- reg = <0x00918000 0x8000>;
- overw_reg = <&ocram 0x00905000 0x13000>;
+ reg = <0x918000 0x8000>;
+ overw_reg = <&ocram 0x905000 0x13000>;
};
intc: interrupt-controller@a01000 {
interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
};
- ocrams_ddr: sram@00900000 {
+ ocrams_ddr: sram@900000 {
compatible = "fsl,ddr-lpm-sram";
- reg = <0x00900000 0x1000>;
+ reg = <0x900000 0x1000>;
clocks = <&clks IMX7D_OCRAM_CLK>;
};
ocram: sram@901000 {
compatible = "mmio-sram";
- reg = <0x00901000 0x1f000>;
+ reg = <0x901000 0x1f000>;
clocks = <&clks IMX7D_OCRAM_CLK>;
};
- ocrams: sram@00180000 {
+ ocrams: sram@180000 {
compatible = "fsl,lpm-sram";
- reg = <0x00180000 0x8000>;
+ reg = <0x180000 0x8000>;
clocks = <&clks IMX7D_OCRAM_S_CLK>;
status = "disabled";
};
overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
};
- ocrams_mf: sram-mf@00900000 {
+ ocrams_mf: sram-mf@900000 {
compatible = "fsl,mega-fast-sram";
- reg = <0x00900000 0x20000>;
+ reg = <0x900000 0x20000>;
clocks = <&clks IMX7D_OCRAM_CLK>;
};