-&fec2 {
- status = "disable";
-};
-
&usbotg1 {
dr_mode = "peripheral";
};
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+ (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
+ IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
+
return set_clk_enet(ENET_125MHZ);
}
CONFIG_PHYLIB=y
CONFIG_PHY_BROADCOM=y
CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
+CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PHYLIB=y
CONFIG_PHY_BROADCOM=y
CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
+CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+/* Default ETH port */
+#define CONFIG_ETHPRIME "eth0"
+
/* I2C configs */
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000