endif
obj-y += busfreq_lpddr2.o busfreq-imx.o busfreq_ddr3.o
AFLAGS_ddr3_freq_imx6.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o ddr3_freq_imx6.o
+AFLAGS_smp_wfe_imx6.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o ddr3_freq_imx6.o smp_wfe_imx6.o
AFLAGS_lpddr2_freq_imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o lpddr2_freq_imx6.o
AFLAGS_ddr3_freq_imx6sx.o :=-Wa,-march=armv7-a
void (*wfe_change_ddr_freq)(u32 cpuid, u32 *ddr_freq_change_done);
void (*imx7_wfe_change_ddr_freq)(u32 cpuid, u32 ocram_base);
-extern void wfe_ddr3_freq_change(u32 cpuid, u32 *ddr_freq_change_done);
+extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done);
extern void imx7_smp_wfe(u32 cpuid, u32 ocram_base);
-extern unsigned long wfe_ddr3_freq_change_start
- asm("wfe_ddr3_freq_change_start");
-extern unsigned long wfe_ddr3_freq_change_end asm("wfe_ddr3_freq_change_end");
+extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start");
+extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end");
extern void __iomem *imx_scu_base;
#endif
wfe_freq_change_iram_base += FNCPY_ALIGN -
((uintptr_t)wfe_freq_change_iram_base % (FNCPY_ALIGN));
- wfe_code_size = (&wfe_ddr3_freq_change_end -
- &wfe_ddr3_freq_change_start) *4;
+ wfe_code_size = (&wfe_smp_freq_change_end -
+ &wfe_smp_freq_change_start) *4;
wfe_change_ddr_freq = (void *)fncpy((void *)wfe_freq_change_iram_base,
- &wfe_ddr3_freq_change, wfe_code_size);
+ &wfe_smp_freq_change, wfe_code_size);
/*
* Store the variable used to communicate
#if !defined(CONFIG_SOC_IMX6Q)
u32 mx6_ddr3_freq_change_start, mx6_ddr3_freq_change_end;
-u32 wfe_ddr3_freq_change_start, wfe_ddr3_freq_change_end;
+u32 wfe_smp_freq_change_start, wfe_smp_freq_change_end;
void mx6_ddr3_freq_change(u32 freq, void *ddr_settings,
bool dll_mode, void *iomux_offsets) {}
-void wfe_ddr3_freq_change(u32 cpuid, u32 *ddr_freq_change_done) {}
+void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done) {}
#endif
#if !defined(CONFIG_SOC_IMX7D)
#define ANADIG_DIGPROG 0x260
.extern iram_tlb_phys_addr
-#ifdef CONFIG_SMP
-.extern imx_scu_base
-#endif
.globl mx6_ddr3_freq_change_start
.globl mx6_ddr3_freq_change_end
-.globl wfe_ddr3_freq_change_start
-.globl wfe_ddr3_freq_change_end
.align 3
*/
.ltorg
mx6_ddr3_freq_change_end:
-
-#ifdef CONFIG_SMP
- .align 3
-
-ENTRY(wfe_ddr3_freq_change)
-wfe_ddr3_freq_change_start:
- push {r4 - r11, lr}
-
- mov r6, r0
- mov r7, r1
-
- dsb
- isb
-
- disable_l1_dcache
-
- isb
-
- /* Turn off SMP bit. */
- mrc p15, 0, r8, c1, c0, 1
- bic r8, r8, #0x40
- mcr p15, 0, r8, c1, c0, 1
-
- isb
-
- /* Inform the SCU we are going to enter WFE. */
- push {r0 - r11, lr}
-
- ldr r0,=imx_scu_base
- ldr r0, [r0]
- mov r1, #SCU_PM_DORMANT
- ldr r3, =scu_power_mode
- mov lr, pc
- mov pc, r3
-
- pop {r0 - r11, lr}
-
-go_back_wfe:
- wfe
-
- ldr r3, [r7]
- cmp r3, #1
- beq go_back_wfe
-
- /* Turn ON SMP bit. */
- mrc p15, 0, r8, c1, c0, 1
- orr r8, r8, #0x40
- mcr p15, 0, r8, c1, c0, 1
-
- isb
- /* Enable L1 data cache. */
- mrc p15, 0, r8, c1, c0, 0
- orr r8, r8, #0x4
- mcr p15, 0, r8, c1, c0, 0
- isb
-
- /* Inform the SCU we have exited WFE. */
- push {r0 - r11, lr}
-
- ldr r0,=imx_scu_base
- ldr r0, [r0]
- mov r1, #SCU_PM_NORMAL
- ldr r3, =scu_power_mode
- mov lr, pc
- mov pc, r3
-
- pop {r0 - r11, lr}
-
- /* Pop all saved registers. */
- pop {r4 - r11, lr}
- mov pc, lr
- .ltorg
-wfe_ddr3_freq_change_end:
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/linkage.h>
+#include <asm/smp_scu.h>
+#include "hardware.h"
+
+#ifdef CONFIG_SMP
+.extern imx_scu_base
+#endif
+
+.globl wfe_smp_freq_change_start
+.globl wfe_smp_freq_change_end
+
+#ifdef CONFIG_SMP
+
+ .align 3
+
+ .macro disable_l1_dcache
+
+ /*
+ * Flush all data from the L1 data cache before disabling
+ * SCTLR.C bit.
+ */
+ push {r0 - r11, lr}
+
+ ldr r7, =v7_flush_kern_cache_all
+ mov lr, pc
+ mov pc, r7
+ pop {r0 - r11, lr}
+
+ /* disable d-cache */
+ mrc p15, 0, r6, c1, c0, 0
+ bic r6, r6, #0x4
+ mcr p15, 0, r6, c1, c0, 0
+ dsb
+ isb
+
+ push {r0 - r11, lr}
+
+ ldr r7, =v7_flush_kern_cache_all
+ mov lr, pc
+ mov pc, r7
+ pop {r0 - r11, lr}
+
+ .endm
+
+ENTRY(wfe_smp_freq_change)
+wfe_smp_freq_change_start:
+ push {r4 - r11, lr}
+
+ mov r6, r0
+ mov r7, r1
+
+ dsb
+ isb
+
+ disable_l1_dcache
+
+ isb
+
+ /* Turn off SMP bit. */
+ mrc p15, 0, r8, c1, c0, 1
+ bic r8, r8, #0x40
+ mcr p15, 0, r8, c1, c0, 1
+
+ isb
+
+ /* Inform the SCU we are going to enter WFE. */
+ push {r0 - r11, lr}
+
+ ldr r0,=imx_scu_base
+ ldr r0, [r0]
+ mov r1, #SCU_PM_DORMANT
+ ldr r3, =scu_power_mode
+ mov lr, pc
+ mov pc, r3
+
+ pop {r0 - r11, lr}
+
+go_back_wfe:
+ wfe
+
+ ldr r3, [r7]
+ cmp r3, #1
+ beq go_back_wfe
+
+ /* Turn ON SMP bit. */
+ mrc p15, 0, r8, c1, c0, 1
+ orr r8, r8, #0x40
+ mcr p15, 0, r8, c1, c0, 1
+
+ isb
+ /* Enable L1 data cache. */
+ mrc p15, 0, r8, c1, c0, 0
+ orr r8, r8, #0x4
+ mcr p15, 0, r8, c1, c0, 0
+ isb
+
+ /* Inform the SCU we have exited WFE. */
+ push {r0 - r11, lr}
+
+ ldr r0,=imx_scu_base
+ ldr r0, [r0]
+ mov r1, #SCU_PM_NORMAL
+ ldr r3, =scu_power_mode
+ mov lr, pc
+ mov pc, r3
+
+ pop {r0 - r11, lr}
+
+ /* Pop all saved registers. */
+ pop {r4 - r11, lr}
+ mov pc, lr
+ .ltorg
+wfe_smp_freq_change_end:
+#endif
projects / linux.git / commitdiff