MLK-13580 ARM: imx: update DGO register to SNVS domain on i.MX7ULP

On i.MX7ULP, the resume entry and parameter are saved
in DGO_GP registers, it has two power domains, one
is normal domain, the other is SNVS domain, if M4 also
enters VLLS mode, DGO needs to be updated into SNVS
domain to avoid power lost and lead to resume fail.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

diff --git a/arch/arm/mach-imx/suspend-imx7ulp.S b/arch/arm/mach-imx/suspend-imx7ulp.S
index 40a3ee3..bb250c6 100644 (file)
--- a/arch/arm/mach-imx/suspend-imx7ulp.S
+++ b/arch/arm/mach-imx/suspend-imx7ulp.S
@@ -283,6 +283,19 @@ ENTRY(imx7ulp_suspend)
        /* store physical resume addr and pm_info address. */
        str     r9, [r11, #DGO_GPR3]
        str     r1, [r11, #DGO_GPR4]
+       ldr     r7, [r11, #DGO_CTRL0]
+       orr     r7, r7, #0xc
+       str     r7, [r11, #DGO_CTRL0]
+wait_dgo:
+       ldr     r7, [r11, #DGO_CTRL0]
+       and     r7, r7, #0x18000
+       cmp     r7, #0x18000
+       bne     wait_dgo
+
+       ldr     r7, [r11, #DGO_CTRL0]
+       orr     r7, r7, #0x18000
+       bic     r7, r7, #0xc
+       str     r7, [r11, #DGO_CTRL0]
 
        disable_l1_dcache