arm64: dts: imx8qm: add emvsim device node

Add emvsim device node for imx8qm mek.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
(cherry picked from commit e4586a8fddc499296abc1442ff3291559fb77e97)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 5c4e3e2..4cb11cd 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -113,6 +113,21 @@ dma_subsys: bus@5a000000 {
                status = "disabled";
        };
 
+       emvsim0: sim0@5a0d0000 {
+               compatible = "fsl,imx8-emvsim";
+               reg = <0x5a0d0000 0x10000>;
+               interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&emvsim0_lpcg 0>,
+                        <&emvsim0_lpcg 1>;
+               clock-names = "sim", "ipg";
+               assigned-clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd IMX_SC_R_EMVSIM_0>, <&pd IMX_SC_R_BOARD_R2>;
+               power-domain-names = "sim_pd", "sim_aux_pd";
+               status = "disabled";
+       };
+
        edma2: dma-controller@5a1f0000 {
                compatible = "fsl,imx8qm-edma";
                reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
@@ -224,6 +239,18 @@ dma_subsys: bus@5a000000 {
                power-domains = <&pd IMX_SC_R_UART_3>;
        };
 
+       emvsim0_lpcg: clock-controller@5a4d0000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x5a4d0000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>,
+                        <&dma_ipg_clk>;
+               bit-offset = <0 16>;
+               clock-output-names = "emvsim0_lpcg_clk",
+                                    "emvsim0_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_EMVSIM_0>;
+       };
+
        adc0: adc@5a880000 {
                compatible = "fsl,imx8qxp-adc";
                reg = <0x5a880000 0x10000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 525d353..a01626f 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -494,6 +494,12 @@
        };
 };
 
+&emvsim0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sim0>;
+       status = "okay";
+};
+
 &lpuart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lpuart0>;
@@ -1070,6 +1076,16 @@
                >;
        };
 
+       pinctrl_sim0: sim0grp {
+               fsl,pins = <
+                       IMX8QM_SIM0_CLK_DMA_SIM0_CLK            0xc0000021
+                       IMX8QM_SIM0_IO_DMA_SIM0_IO              0xc2000021
+                       IMX8QM_SIM0_PD_DMA_SIM0_PD              0xc0000021
+                       IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN  0xc0000021
+                       IMX8QM_SIM0_RST_DMA_SIM0_RST            0xc0000021
+               >;
+       };
+
        pinctrl_lpuart0: lpuart0grp {
                fsl,pins = <
                        IMX8QM_UART0_RX_DMA_UART0_RX                            0x06000020