perf/x86: Expose CPUID enumeration bits for arch LBR

The LBR capabilities of Architecture LBR are retrieved from the CPUID
enumeration once at boot time. The capabilities have to be saved for
future usage.

Several new fields are added into structure x86_pmu to indicate the
capabilities. The fields will be used in the following patches.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1593780569-62993-9-git-send-email-kan.liang@linux.intel.com

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 7dbf148..cc81177 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -693,6 +693,19 @@ struct x86_pmu {
        bool            lbr_double_abort;          /* duplicated lbr aborts */
        bool            lbr_pt_coexist;            /* (LBR|BTS) may coexist with PT */
 
+       /*
+        * Intel Architectural LBR CPUID Enumeration
+        */
+       unsigned int    lbr_depth_mask:8;
+       unsigned int    lbr_deep_c_reset:1;
+       unsigned int    lbr_lip:1;
+       unsigned int    lbr_cpl:1;
+       unsigned int    lbr_filter:1;
+       unsigned int    lbr_call_stack:1;
+       unsigned int    lbr_mispred:1;
+       unsigned int    lbr_timed_lbr:1;
+       unsigned int    lbr_br_type:1;
+
        void            (*lbr_reset)(void);
        void            (*lbr_read)(struct cpu_hw_events *cpuc);
        void            (*lbr_save)(void *ctx);

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 2df7073..9ffce7d 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -142,6 +142,46 @@ union cpuid10_edx {
        unsigned int full;
 };
 
+/*
+ * Intel Architectural LBR CPUID detection/enumeration details:
+ */
+union cpuid28_eax {
+       struct {
+               /* Supported LBR depth values */
+               unsigned int    lbr_depth_mask:8;
+               unsigned int    reserved:22;
+               /* Deep C-state Reset */
+               unsigned int    lbr_deep_c_reset:1;
+               /* IP values contain LIP */
+               unsigned int    lbr_lip:1;
+       } split;
+       unsigned int            full;
+};
+
+union cpuid28_ebx {
+       struct {
+               /* CPL Filtering Supported */
+               unsigned int    lbr_cpl:1;
+               /* Branch Filtering Supported */
+               unsigned int    lbr_filter:1;
+               /* Call-stack Mode Supported */
+               unsigned int    lbr_call_stack:1;
+       } split;
+       unsigned int            full;
+};
+
+union cpuid28_ecx {
+       struct {
+               /* Mispredict Bit Supported */
+               unsigned int    lbr_mispred:1;
+               /* Timed LBRs Supported */
+               unsigned int    lbr_timed_lbr:1;
+               /* Branch Type Field Supported */
+               unsigned int    lbr_br_type:1;
+       } split;
+       unsigned int            full;
+};
+
 struct x86_pmu_capability {
        int             version;
        int             num_counters_gp;