LF-1262 arm64: dts: imx8mp: Add cpufreq support

Add A53 OPP table and regulator to support cpufreq.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index c16d4da..2e5c4ea 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -45,6 +45,22 @@
        };
 };
 
+&A53_0 {
+       cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+       cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+       cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+       cpu-supply = <&buck2_reg>;
+};
+
 &eqos {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_eqos>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index b466df7..1f92696 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -49,6 +49,9 @@
                        reg = <0x0>;
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
@@ -60,6 +63,7 @@
                        reg = <0x1>;
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
+                       operating-points-v2 = <&a53_opp_table>;
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
@@ -71,6 +75,7 @@
                        reg = <0x2>;
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
+                       operating-points-v2 = <&a53_opp_table>;
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
@@ -82,6 +87,7 @@
                        reg = <0x3>;
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
+                       operating-points-v2 = <&a53_opp_table>;
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
@@ -92,6 +98,35 @@
                };
        };
 
+       a53_opp_table: opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <850000>;
+                       opp-supported-hw = <0x8a0>, <0x7>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+
+               opp-1600000000 {
+                       opp-hz = /bits/ 64 <1600000000>;
+                       opp-microvolt = <950000>;
+                       opp-supported-hw = <0xa0>, <0x7>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <1000000>;
+                       opp-supported-hw = <0x20>, <0x3>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+       };
+
        osc_32k: clock-osc-32k {
                compatible = "fixed-clock";
                #clock-cells = <0>;