Ensure ipg clock enable during .uart_resume_port() that call set
ops->set_mctrl() before ops->startup().
BuildInfo:
- SCFW
daf9431c, IMX-MKIMAGE
1c6fc7d8, ATF
f2547fb
- U-Boot
2017.03-00097-gd7599cf
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
{
struct lpuart_port *sport = dev_get_drvdata(dev);
struct tty_port *port = &sport->port.state->port;
+ bool ipgclk_on = false;
int ret;
if (sport->lpuart32)
if (uart_console(&sport->port) ||
(sport->port.irq_wake && tty_port_initialized(port))) {
+ ipgclk_on = true;
ret = clk_prepare_enable(sport->per_clk);
if (ret)
return ret;
- } else {
- clk_disable_unprepare(sport->ipg_clk);
}
uart_resume_port(&lpuart_reg, &sport->port);
+ if (!ipgclk_on)
+ clk_disable_unprepare(sport->ipg_clk);
+
return 0;
}