MLK-19252-7 drm/bridge: sec-dsim: workaround for 720p@60Hz on 4 lanes

For the CEA standard mode '1280x720@60Hz', the standard HFP value
is not suitable for the DSI peripheral which works with Non-burst
with Sync Pulse mode with 4 data lanes enabled. And this commit is
a workaround to plus 2 to the original HFP value to make this case
can display correctly.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 8b39ff24f89c5a9d21459ab5af47259060185b0a)
(cherry picked from commit 56c91a7ee40f866ae770b2f20b3ea623c6c2f0cc)
(cherry picked from commit cff6ad221228f69728c689a8ca7359eaa642573c)

diff --git a/drivers/gpu/drm/bridge/sec-dsim.c b/drivers/gpu/drm/bridge/sec-dsim.c
index 70650b0..5f3a660 100644 (file)
--- a/drivers/gpu/drm/bridge/sec-dsim.c
+++ b/drivers/gpu/drm/bridge/sec-dsim.c
@@ -1330,6 +1330,23 @@ static void sec_mipi_dsim_bridge_mode_set(struct drm_bridge *bridge,
         * so it is called not every time atomic commit.
         */
 
+       /* workaround for CEA standard mode "1280x720@60"
+        * display on 4 data lanes with Non-burst with sync
+        * pulse DSI mode, since use the standard horizontal
+        * timings cannot display correctly. And this code
+        * cannot be put into the dsim Bridge's mode_fixup,
+        * since the DSI device lane number change always
+        * happens after that.
+        */
+       if (!strcmp(mode->name, "1280x720") &&
+           mode->vrefresh == 60            &&
+           dsim->lanes == 4                &&
+           dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
+               adjusted_mode->hsync_start += 2;
+               adjusted_mode->hsync_end   += 2;
+               adjusted_mode->htotal      += 2;
+       }
+
        drm_display_mode_to_videomode(adjusted_mode, &dsim->vmode);
 }