int imx7ulp_set_lpm(enum imx7ulp_cpu_pwr_mode mode);
#ifdef CONFIG_HAVE_IMX_MMDC
int imx_mmdc_get_ddr_type(void);
+int imx_mmdc_get_lpddr2_2ch_mode(void);
#else
static inline int imx_mmdc_get_ddr_type(void) { return 0; }
+static inline int imx_mmdc_get_lpddr2_2ch_mode(void) { return 0; }
#endif
#ifdef CONFIG_HAVE_IMX_DDRC
int imx_ddrc_get_ddr_type(void);
#define MMDC_MDMISC 0x18
#define BM_MMDC_MDMISC_DDR_TYPE 0x18
#define BP_MMDC_MDMISC_DDR_TYPE 0x3
+#define BM_MMDC_MDMISC_LPDDR2_2CH 0x4
+#define BP_MMDC_MDMISC_LPDDR2_2CH 0x2
static int ddr_type;
+static int lpddr2_2ch_mode;
static int imx_mmdc_probe(struct platform_device *pdev)
{
val = readl_relaxed(reg);
ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >>
BP_MMDC_MDMISC_DDR_TYPE;
+ /* Get lpddr2 2ch-mode */
+ lpddr2_2ch_mode = (val & BM_MMDC_MDMISC_LPDDR2_2CH) >>
+ BP_MMDC_MDMISC_LPDDR2_2CH;
reg = mmdc_base + MMDC_MAPSR;
return ddr_type;
}
+int imx_mmdc_get_lpddr2_2ch_mode(void)
+{
+ return lpddr2_2ch_mode;
+}
+
static const struct of_device_id imx_mmdc_dt_ids[] = {
{ .compatible = "fsl,imx6q-mmdc", },
{ /* sentinel */ }
#define IMX_DDR_TYPE_LPDDR3 2
#define IMX_MMDC_DDR_TYPE_LPDDR3 3
+#define IMX_LPDDR2_1CH_MODE 0
+#define IMX_LPDDR2_2CH_MODE 1
+
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;