MLK-16804-05 driver: soc: add the irq affinity call for child irqchip on imx8mq
authorBai Ping <ping.bai@nxp.com>
Wed, 8 Nov 2017 09:55:20 +0000 (17:55 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 20:46:54 +0000 (15:46 -0500)
On i.MX8MQ, we need the handle the correspoding IMR registers in gpc
to make sure the IRQ affinity to the specific core can be wakeup
successfully from power down idle state.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
drivers/soc/imx/gpc-psci.c

index a7c1f58..49ad145 100644 (file)
@@ -15,6 +15,7 @@
 
 #include <linux/arm-smccc.h>
 #include <linux/clk.h>
+#include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -85,6 +86,23 @@ static int imx_gpc_psci_irq_set_wake(struct irq_data *d, unsigned int on)
        return 0;
 }
 
+static int imx_gpc_psci_irq_set_affinity(struct irq_data *d,
+                                        const struct cpumask *dest, bool force)
+{
+       /* parse the cpu of irq affinity */
+       struct arm_smccc_res res;
+       unsigned int cpu = cpumask_any_and(dest, cpu_online_mask);
+
+       irq_chip_set_affinity_parent(d, dest, force);
+
+       spin_lock(&gpc_psci_lock);
+       arm_smccc_smc(FSL_SIP_GPC, 0x4, d->hwirq,
+                     cpu, 0, 0, 0, 0, &res);
+       spin_unlock(&gpc_psci_lock);
+
+       return 0;
+}
+
 static struct irq_chip imx_gpc_psci_chip = {
        .name                   = "GPC-PSCI",
        .irq_eoi                = irq_chip_eoi_parent,
@@ -92,9 +110,7 @@ static struct irq_chip imx_gpc_psci_chip = {
        .irq_unmask             = imx_gpc_psci_irq_unmask,
        .irq_retrigger          = irq_chip_retrigger_hierarchy,
        .irq_set_wake           = imx_gpc_psci_irq_set_wake,
-#ifdef CONFIG_SMP
-       .irq_set_affinity       = irq_chip_set_affinity_parent,
-#endif
+       .irq_set_affinity       = imx_gpc_psci_irq_set_affinity,
 };
 
 static int imx_gpc_psci_domain_translate(struct irq_domain *d,