arm64: dts: imx8m: Add NOC nodes
authorLeonard Crestez <leonard.crestez@nxp.com>
Tue, 23 Jun 2020 09:36:09 +0000 (12:36 +0300)
committerDong Aisheng <aisheng.dong@nxp.com>
Mon, 14 Dec 2020 03:22:45 +0000 (11:22 +0800)
Add nodes for the main interconnect of the imx8m series chips.

These nodes are bound to by devfreq and interconnect drivers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Martin Kepplinger <martin.kepplinger@puri.sm>
arch/arm64/boot/dts/freescale/imx8mm.dtsi
arch/arm64/boot/dts/freescale/imx8mn.dtsi
arch/arm64/boot/dts/freescale/imx8mq.dtsi

index 9cd1a9e..3d652e7 100755 (executable)
 
                };
 
+               noc: interconnect@32700000 {
+                       compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
+                       reg = <0x32700000 0x100000>;
+                       clocks = <&clk IMX8MM_CLK_NOC>;
+                       fsl,ddrc = <&ddrc>;
+                       #interconnect-cells = <1>;
+                       operating-points-v2 = <&noc_opp_table>;
+
+                       noc_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-150M {
+                                       opp-hz = /bits/ 64 <150000000>;
+                               };
+                               opp-375M {
+                                       opp-hz = /bits/ 64 <375000000>;
+                               };
+                               opp-750M {
+                                       opp-hz = /bits/ 64 <750000000>;
+                               };
+                       };
+               };
+
                aips4: bus@32c00000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        reg = <0x32c00000 0x400000>;
index 145b519..ea4c94c 100644 (file)
 
                };
 
+               noc: interconnect@32700000 {
+                       compatible = "fsl,imx8mn-noc", "fsl,imx8m-noc";
+                       reg = <0x32700000 0x100000>;
+                       clocks = <&clk IMX8MN_CLK_NOC>;
+                       fsl,ddrc = <&ddrc>;
+                       #interconnect-cells = <1>;
+                       operating-points-v2 = <&noc_opp_table>;
+
+                       noc_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-100M {
+                                       opp-hz = /bits/ 64 <100000000>;
+                               };
+                               opp-600M {
+                                       opp-hz = /bits/ 64 <600000000>;
+                               };
+                               opp-800M {
+                                       opp-hz = /bits/ 64 <800000000>;
+                               };
+                       };
+               };
+
                aips4: bus@32c00000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        reg = <0x32c00000 0x400000>;
index 175dbe4..c256789 100755 (executable)
                        };
                };
 
+               noc: interconnect@32700000 {
+                       compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
+                       reg = <0x32700000 0x100000>;
+                       clocks = <&clk IMX8MQ_CLK_NOC>;
+                       fsl,ddrc = <&ddrc>;
+                       #interconnect-cells = <1>;
+                       operating-points-v2 = <&noc_opp_table>;
+
+                       noc_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-133M {
+                                       opp-hz = /bits/ 64 <133333333>;
+                               };
+                               opp-400M {
+                                       opp-hz = /bits/ 64 <400000000>;
+                               };
+                               opp-800M {
+                                       opp-hz = /bits/ 64 <800000000>;
+                               };
+                       };
+               };
+
                bus@32c00000 { /* AIPS4 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        reg = <0x32c00000 0x400000>;