drm/amdgpu: remove unnecessary conversion to bool
authorNirmoy Das <nirmoy.das@amd.com>
Mon, 20 Jan 2020 12:54:30 +0000 (13:54 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 22 Jan 2020 21:55:27 +0000 (16:55 -0500)
Better clean that up before some automation starts to complain about it

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
25 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
drivers/gpu/drm/amd/amdgpu/si_dma.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
drivers/gpu/drm/amd/amdgpu/vega10_ih.c

index 82155ac..12247a3 100644 (file)
@@ -527,7 +527,7 @@ static int acp_set_powergating_state(void *handle,
                                     enum amd_powergating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = state == AMD_PG_STATE_GATE ? true : false;
+       bool enable = (state == AMD_PG_STATE_GATE);
 
        if (adev->powerplay.pp_funcs &&
                adev->powerplay.pp_funcs->set_powergating_by_smu)
index 64b1b2d..990f8e6 100644 (file)
@@ -985,7 +985,7 @@ static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 {
        struct sysinfo si;
-       bool is_os_64 = (sizeof(void *) == 8) ? true : false;
+       bool is_os_64 = (sizeof(void *) == 8);
        uint64_t total_memory;
        uint64_t dram_size_seven_GB = 0x1B8000000;
        uint64_t dram_size_three_GB = 0xB8000000;
index d9cc746..847ca9b 100644 (file)
@@ -74,9 +74,9 @@ int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
        case CHIP_VEGA20:
        case CHIP_RAVEN:
                athub_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                athub_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index ceb9aa4..921a69a 100644 (file)
@@ -77,9 +77,9 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
        case CHIP_NAVI14:
        case CHIP_NAVI12:
                athub_v2_0_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                athub_v2_0_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index 65885ba..1785fda 100644 (file)
@@ -4229,7 +4229,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
                                          enum amd_powergating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_PG_STATE_GATE);
        switch (adev->asic_type) {
        case CHIP_NAVI10:
        case CHIP_NAVI14:
@@ -4255,7 +4255,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
        case CHIP_NAVI14:
        case CHIP_NAVI12:
                gfx_v10_0_update_gfx_clock_gating(adev,
-                                                state == AMD_CG_STATE_GATE ? true : false);
+                                                state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index f8b1fd6..6558d70 100644 (file)
@@ -4652,7 +4652,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
                                          enum amd_powergating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_PG_STATE_GATE);
 
        switch (adev->asic_type) {
        case CHIP_RAVEN:
@@ -4714,7 +4714,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
        case CHIP_ARCTURUS:
        case CHIP_RENOIR:
                gfx_v9_0_update_gfx_clock_gating(adev,
-                                                state == AMD_CG_STATE_GATE ? true : false);
+                                                state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index a78292d..ff2e6e1 100644 (file)
@@ -690,7 +690,7 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
 
        if (enable) {
                if (jpeg_v2_0_is_idle(handle))
index 2c58939..c6d046d 100644 (file)
@@ -469,7 +469,7 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
        int i;
 
        for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
index adfd8a6..49a3a56 100644 (file)
@@ -523,9 +523,9 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
        case CHIP_RAVEN:
        case CHIP_RENOIR:
                mmhub_v1_0_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                mmhub_v1_0_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index a7cb185..bde1896 100644 (file)
@@ -427,9 +427,9 @@ int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
        case CHIP_NAVI14:
        case CHIP_NAVI12:
                mmhub_v2_0_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                mmhub_v2_0_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index a32c975..a5281df 100644 (file)
@@ -625,9 +625,9 @@ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
        switch (adev->asic_type) {
        case CHIP_ARCTURUS:
                mmhub_v9_4_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                mmhub_v9_4_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index f737ce4..cf557a4 100644 (file)
@@ -426,7 +426,7 @@ static int navi10_ih_set_clockgating_state(void *handle,
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        navi10_ih_update_clockgating_state(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
        return 0;
 }
 
index 2e0f893..2d1bebd 100644 (file)
@@ -950,13 +950,13 @@ static int nv_common_set_clockgating_state(void *handle,
        case CHIP_NAVI14:
        case CHIP_NAVI12:
                adev->nbio.funcs->update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                adev->nbio.funcs->update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                nv_update_hdp_mem_power_gating(adev,
-                                  state == AMD_CG_STATE_GATE ? true : false);
+                                  state == AMD_CG_STATE_GATE);
                nv_update_hdp_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index 27c7001..e55884d 100644 (file)
@@ -2176,9 +2176,9 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
        case CHIP_ARCTURUS:
        case CHIP_RENOIR:
                sdma_v4_0_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                sdma_v4_0_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index 4c6bf1f..67b9830 100644 (file)
@@ -1525,9 +1525,9 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
        case CHIP_NAVI14:
        case CHIP_NAVI12:
                sdma_v5_0_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                sdma_v5_0_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index 9aac9f9..42d5601 100644 (file)
@@ -648,7 +648,7 @@ static int si_dma_set_clockgating_state(void *handle,
        bool enable;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       enable = (state == AMD_CG_STATE_GATE);
 
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
                for (i = 0; i < adev->sdma.num_instances; i++) {
index 317803f..af41ee4 100644 (file)
@@ -1467,38 +1467,38 @@ static int soc15_common_set_clockgating_state(void *handle,
        case CHIP_VEGA12:
        case CHIP_VEGA20:
                adev->nbio.funcs->update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                adev->nbio.funcs->update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_hdp_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_drm_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_drm_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_rom_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                adev->df.funcs->update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        case CHIP_RAVEN:
        case CHIP_RENOIR:
                adev->nbio.funcs->update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                adev->nbio.funcs->update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_hdp_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_drm_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_drm_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                soc15_update_rom_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        case CHIP_ARCTURUS:
                soc15_update_hdp_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
                break;
        default:
                break;
index 01e62fb..0fa8aae 100644 (file)
@@ -763,7 +763,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
 
        if (enable) {
                /* wait for STATUS to clear */
index 217084d..e0aadca 100644 (file)
@@ -1421,7 +1421,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
 
        if (enable) {
                /* wait for STATUS to clear */
index 475ae68..217db18 100644 (file)
@@ -739,7 +739,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
        int i;
 
        if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
index 683701c..3fd102e 100644 (file)
@@ -887,7 +887,7 @@ static int vce_v4_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
        int i;
 
        if ((adev->asic_type == CHIP_POLARIS10) ||
index e654938..1a24fad 100644 (file)
@@ -1346,7 +1346,7 @@ static int vcn_v1_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
 
        if (enable) {
                /* wait for STATUS to clear */
index f4db8af..b8dc136 100644 (file)
@@ -1213,7 +1213,7 @@ static int vcn_v2_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
 
        if (enable) {
                /* wait for STATUS to clear */
index c8b63d5..6970d3a 100644 (file)
@@ -1663,7 +1663,7 @@ static int vcn_v2_5_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+       bool enable = (state == AMD_CG_STATE_GATE);
 
        if (amdgpu_sriov_vf(adev))
                return 0;
index d9e3310..407c609 100644 (file)
@@ -717,7 +717,7 @@ static int vega10_ih_set_clockgating_state(void *handle,
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        vega10_ih_update_clockgating_state(adev,
-                               state == AMD_CG_STATE_GATE ? true : false);
+                               state == AMD_CG_STATE_GATE);
        return 0;
 
 }