Adding HDMI support for splash screen.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
#
-# Copyright 2017 NXP
+# Copyright 2017-2018 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
UBOOTINCLUDE += -I$(srctree)/drivers/video/imx/hdp
obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += hdp_load.o hdp/
+obj-$(CONFIG_VIDEO_IMX8_HDMI) += hdp.o imx8_hdmi.o hdp/
--- /dev/null
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/imx-common/video.h>
+#include <asm/arch/video_common.h>
+#include <imx8_hdmi.h>
+
+int do_hdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ if (argc < 2)
+ return 0;
+
+ if (strncmp(argv[1], "colorbar", 8) == 0) {
+ GraphicDevice *gdev;
+ struct video_mode_settings *vm;
+
+ gdev = imx8m_get_gd();
+ vm = imx8m_get_gmode();
+ imx8m_show_gmode();
+
+ imx8m_create_color_bar(
+ (void *)((uint64_t)gdev->frameAdrs),
+ vm);
+ printf("colorbar test\n");
+ } else if (strncmp(argv[1], "stop", 4) == 0) {
+ imx8_hdmi_disable();
+ printf("stopping hdmi\n");
+ } else {
+ printf("test error argc %d\n", argc);
+ }
+
+ return 0;
+}
+/***************************************************/
+
+U_BOOT_CMD(
+ hdp, CONFIG_SYS_MAXARGS, 1, do_hdp,
+ "hdmi/dp display test commands",
+ "[<command>] ...\n"
+ "colorbar - display a colorbar pattern\n"
+ );
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE.c
+ *
+ ******************************************************************************
+ */
+
+#include "address.h"
+#include "API_AFE.h"
+#include "util.h"
+#ifndef __UBOOT__
+#include <stdio.h>
+#endif
+
+void afe_write(unsigned int offset, unsigned short val)
+{
+#ifdef EXTERNAL_AFE
+ cdn_phapb_write(offset << 2, val);
+#else
+ CDN_API_STATUS sts;
+
+ sts = cdn_api_general_write_register_blocking(
+ ADDR_AFE + (offset << 2), val);
+
+ if (sts != CDN_OK) {
+ printf("CDN_API_General_Write_Register_blocking(0x%.8X, 0x%.8X) returned %d\n",
+ offset,
+ val,
+ (int)sts);
+ }
+#endif
+}
+
+unsigned short afe_read(unsigned int offset)
+{
+ GENERAL_READ_REGISTER_RESPONSE resp;
+
+#ifdef EXTERNAL_AFE
+ cdn_phapb_read(offset << 2, &resp.val);
+#else
+ CDN_API_STATUS sts;
+
+ sts = cdn_api_general_read_register_blocking(
+ ADDR_AFE + (offset << 2), &resp);
+
+ if (sts != CDN_OK) {
+ printf("CDN_API_General_Read_Register_blocking(0x%.8X) returned %d\n",
+ offset,
+ (int)sts);
+ }
+#endif
+ return resp.val;
+}
+
+void set_field_value(reg_field_t *reg_field, u32 value)
+{
+ u8 length;
+ u32 max_value;
+ u32 trunc_val;
+ length = (reg_field->msb - reg_field->lsb + 1);
+
+ max_value = (1 << length) - 1;
+ if (value > max_value) {
+ trunc_val = value;
+ trunc_val &= (1 << length) - 1;
+ printf("set_field_value() Error! Specified value (0x%0X) exceeds field capacity - it will by truncated to 0x%0X (%0d-bit field - max value: %0d dec)\n",
+ value, trunc_val, length, max_value);
+ } else {
+ reg_field->value = value;
+ }
+}
+
+int set_reg_value(reg_field_t reg_field)
+{
+ return reg_field.value << reg_field.lsb;
+}
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_H_
+#define API_AFE_H_
+#include "util.h"
+
+typedef enum {
+ AFE_LINK_RATE_1_6 = 0x6, /* 1.62 Gb/s */
+ AFE_LINK_RATE_2_1 = 0x8, /* 2.16 Gb/s */
+ AFE_LINK_RATE_2_4 = 0x9, /* 2.43 Gb/s */
+ AFE_LINK_RATE_2_7 = 0xA, /* 2.70 Gb/s */
+ AFE_LINK_RATE_3_2 = 0xC, /* 3.24 Gb/s */
+ AFE_LINK_RATE_4_3 = 0x10, /* 4.32 Gb/s */
+ AFE_LINK_RATE_5_4 = 0x14, /* 5.40 Gb/s */
+ AFE_LINK_RATE_8_1 = 0x1E, /* 8.10 Gb/s */
+} ENUM_AFE_LINK_RATE;
+
+/* Some of the PHY programming sequences */
+/* depend on the reference clock frequency. */
+/* Variable of this type is used to control */
+/* the programming flow. */
+typedef enum {
+ REFCLK_24MHZ,
+ REFCLK_27MHZ
+} REFCLK_FREQ;
+
+typedef enum {
+ CLK_RATIO_1_1,
+ CLK_RATIO_5_4,
+ CLK_RATIO_3_2,
+ CLK_RATIO_2_1,
+ CLK_RATIO_1_2,
+ CLK_RATIO_5_8,
+ CLK_RATIO_3_4
+} clk_ratio_t;
+
+typedef struct {
+ u32 value;
+ u8 lsb;
+ u8 msb;
+} reg_field_t;
+
+unsigned char AFE_check_rate_supported(ENUM_AFE_LINK_RATE rate);
+void afe_write(unsigned int offset, unsigned short val);
+unsigned short afe_read(unsigned int offset);
+void AFE_init(int num_lanes, ENUM_AFE_LINK_RATE link_rate);
+void AFE_power(int num_lanes, ENUM_AFE_LINK_RATE link_rate);
+
+/*extern int cdn_phapb_read(unsigned int addr, unsigned int *value);*/
+/*extern int cdn_phapb_write(unsigned int addr, unsigned int value);*/
+void set_field_value(reg_field_t *reg_field, u32 value);
+int set_reg_value(reg_field_t reg_field);
+
+#endif
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_t28hpc_hdmitx.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_AFE_t28hpc_hdmitx.h"
+#include "API_AFE.h"
+#include "externs.h"
+
+#ifndef DEBUG
+static inline void write16(uint32_t addr, uint16_t val)
+{
+ afe_write(addr, val);
+}
+
+static inline uint16_t read16(uint32_t addr)
+{
+ return afe_read(addr);
+}
+#else
+#define write16(addr, val) __write16(addr, val, __LINE__)
+static inline void __write16(uint32_t addr, uint16_t val, int line)
+{
+ afe_write(addr, val);
+ debug("write16():%4d Writting value 0x%04X at address 0x%05X (0x%04X)\n",
+ line, val, (0x20000 * 4) + (addr << 2), addr);
+}
+#define read16(addr) __read16(addr, __LINE__)
+static inline uint16_t __read16(uint32_t addr, int line)
+{
+ debug("read16():%5d Reading from address 0x%05X (0x%04X)\n",
+ line, (0x20000 * 4) + (addr << 2), addr);
+ return afe_read(addr);
+}
+
+#endif
+
+static char inside(u32 value, u32 left_sharp_corner,
+ u32 right_sharp_corner)
+{
+ if (value < left_sharp_corner)
+ return false;
+ if (value > right_sharp_corner)
+ return false;
+ return true;
+}
+
+void aux_cfg_t28hpc(void)
+{
+ write16(0x5025, 0x0001);
+
+ write16(0x5024, 36);
+
+ write16(0x5021, 0x0100);
+ write16(0x5021, 0x0300);
+ write16(0x5026, 0x0000);
+ write16(0x5020, 0x2008);
+ write16(0x5020, 0x2018);
+ write16(0x5020, 0xA018);
+ write16(0x5021, 0x030C);
+ write16(0x5029, 0x0000);
+ write16(0x5027, 0x4001);
+ write16(0x5020, 0xA098);
+ write16(0x5020, 0xA198);
+ write16(0x5021, 0x030D);
+ write16(0x5021, 0x030F);
+}
+
+int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp,
+ VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy)
+{
+ const int phy_reset_workaround = 1;
+ unsigned int vco_freq;
+ unsigned char k;
+ uint32_t reg_val;
+ uint32_t pixel_freq_khz = vic_table[vic_mode][PIXEL_FREQ_KHZ];
+ uint32_t character_clock_ratio_num = 1;
+ uint32_t character_clock_ratio_den = 1;
+ uint32_t character_freq_khz;
+ const unsigned int refclk_freq_khz = 27000;
+ unsigned int ftemp, ftemp2;
+
+ clk_ratio_t clk_ratio = 0;
+ reg_field_t cmnda_pll0_hs_sym_div_sel;
+ reg_field_t cmnda_pll0_ip_div;
+ reg_field_t cmnda_pll0_fb_div_low;
+ reg_field_t cmnda_pll0_fb_div_high;
+ reg_field_t cmn_ref_clk_dig_div;
+ reg_field_t divider_scaler;
+ reg_field_t cmnda_hs_clk_0_sel;
+ reg_field_t cmnda_hs_clk_1_sel;
+ reg_field_t tx_subrate;
+ reg_field_t voltage_to_current_coarse;
+ reg_field_t voltage_to_current;
+ reg_field_t ndac_ctrl;
+ reg_field_t pmos_ctrl;
+ reg_field_t ptat_ndac_ctrl;
+ reg_field_t charge_pump_gain;
+ reg_field_t vco_ring_select;
+ reg_field_t pll_feedback_divider_total;
+ reg_field_t cmnda_pll0_pxdiv_high;
+ reg_field_t cmnda_pll0_pxdiv_low;
+ reg_field_t coarse_code;
+ reg_field_t v2i_code;
+ reg_field_t vco_cal_code;
+
+ cmnda_pll0_fb_div_high.value = 0x00A;
+ ftemp = pixel_freq_khz;
+
+ debug(" VIC %d, pixel clock %u kHz\n", vic_mode, ftemp);
+
+ /* Set field position */
+ cmnda_pll0_hs_sym_div_sel.msb = 9;
+ cmnda_pll0_hs_sym_div_sel.lsb = 8;
+ cmnda_pll0_ip_div.msb = 7;
+ cmnda_pll0_ip_div.lsb = 0;
+ cmnda_pll0_fb_div_low.msb = 9;
+ cmnda_pll0_fb_div_low.lsb = 0;
+ cmnda_pll0_fb_div_high.msb = 9;
+ cmnda_pll0_fb_div_high.lsb = 0;
+ cmn_ref_clk_dig_div.msb = 13;
+ cmn_ref_clk_dig_div.lsb = 12;
+ divider_scaler.msb = 14;
+ divider_scaler.lsb = 12;
+ cmnda_hs_clk_0_sel.msb = 1;
+ cmnda_hs_clk_0_sel.lsb = 0;
+ cmnda_hs_clk_1_sel.msb = 1;
+ cmnda_hs_clk_1_sel.lsb = 0;
+ tx_subrate.msb = 2;
+ tx_subrate.lsb = 0;
+ voltage_to_current_coarse.msb = 2;
+ voltage_to_current_coarse.lsb = 0;
+ voltage_to_current.msb = 5;
+ voltage_to_current.lsb = 4;
+ ndac_ctrl.msb = 11;
+ ndac_ctrl.lsb = 8;
+ pmos_ctrl.msb = 7;
+ pmos_ctrl.lsb = 0;
+ ptat_ndac_ctrl.msb = 5;
+ ptat_ndac_ctrl.lsb = 0;
+ charge_pump_gain.msb = 8;
+ charge_pump_gain.lsb = 0;
+ vco_ring_select.msb = 12;
+ vco_ring_select.lsb = 12;
+ pll_feedback_divider_total.msb = 9;
+ pll_feedback_divider_total.lsb = 0;
+ cmnda_pll0_pxdiv_high.msb = 9;
+ cmnda_pll0_pxdiv_high.lsb = 0;
+ cmnda_pll0_pxdiv_low.msb = 9;
+ cmnda_pll0_pxdiv_low.lsb = 0;
+ coarse_code.msb = 7;
+ coarse_code.lsb = 0;
+ v2i_code.msb = 3;
+ v2i_code.lsb = 0;
+ vco_cal_code.msb = 8;
+ vco_cal_code.lsb = 0;
+
+ if (phy_reset_workaround) {
+ /* register PHY_PMA_ISOLATION_CTRL */
+ write16(0xC81F, 0xD000); /* enable PHY iso mode only for CMN */
+ /* register PHY_PMA_ISO_PLL_CTRL1 */
+ reg_val = read16(0xC812);
+ reg_val &= 0xFF00;
+ reg_val |= 0x0012;
+ /* set pll0_clk_datart1_div/pll0_clk_datart0_div dividers */
+ write16(0xC812, reg_val);
+ /* register PHY_ISO_CMN_CTRL */
+ /* assert PHY reset from isolation register */
+ write16(0xC010, 0x0000);
+ /* register PHY_PMA_ISO_CMN_CTRL */
+ write16(0xC810, 0x0000); /* assert PMA CMN reset */
+ /* register XCVR_DIAG_BIDI_CTRL */
+ for (k = 0; k < num_lanes; k++)
+ write16(0x40E8 | (k << 9), 0x00FF);
+ }
+ /*---------------------------------------------------------------
+ * Describing Task phy_cfg_hdp
+ * --------------------------------------------------------------*/
+ /* register PHY_PMA_CMN_CTRL1 */
+ reg_val = read16(0xC800);
+ reg_val &= 0xFFF7;
+ reg_val |= 0x0008;
+ write16(0xC800, reg_val);
+
+ /* register CMN_DIAG_PLL0_TEST_MODE */
+ write16(0x01C4, 0x0020);
+ /* register CMN_PSM_CLK_CTRL */
+ write16(0x0061, 0x0016);
+
+ switch (format) {
+ case YCBCR_4_2_2:
+ clk_ratio = CLK_RATIO_1_1;
+ character_clock_ratio_num = 1;
+ character_clock_ratio_den = 1;
+ break;
+ case YCBCR_4_2_0:
+ switch (bpp) {
+ case 8:
+ clk_ratio = CLK_RATIO_1_2;
+ character_clock_ratio_num = 1;
+ character_clock_ratio_den = 2;
+ break;
+ case 10:
+ clk_ratio = CLK_RATIO_5_8;
+ character_clock_ratio_num = 5;
+ character_clock_ratio_den = 8;
+ break;
+ case 12:
+ clk_ratio = CLK_RATIO_3_4;
+ character_clock_ratio_num = 3;
+ character_clock_ratio_den = 4;
+ break;
+ case 16:
+ clk_ratio = CLK_RATIO_1_1;
+ character_clock_ratio_num = 1;
+ character_clock_ratio_den = 1;
+ break;
+ default:
+ debug("Invalid ColorDepth\n");
+ }
+ break;
+
+ default:
+ switch (bpp) {
+ /* Assume RGB */
+ case 10:
+ clk_ratio = CLK_RATIO_5_4;
+ character_clock_ratio_num = 5;
+ character_clock_ratio_den = 4;
+ break;
+ case 12:
+ clk_ratio = CLK_RATIO_3_2;
+ character_clock_ratio_num = 3;
+ character_clock_ratio_den = 2;
+ break;
+ case 16:
+ clk_ratio = CLK_RATIO_2_1;
+ character_clock_ratio_num = 2;
+ character_clock_ratio_den = 1;
+ break;
+ default:
+ clk_ratio = CLK_RATIO_1_1;
+ character_clock_ratio_num = 1;
+ character_clock_ratio_den = 1;
+ }
+ }
+
+ character_freq_khz = pixel_freq_khz *
+ character_clock_ratio_num / character_clock_ratio_den;
+ ftemp = pixel_freq_khz;
+ ftemp2 = character_freq_khz;
+ debug("Pixel clock frequency: %u kHz, character clock frequency: %u, color depth is %0d-bit.\n",
+ ftemp, ftemp2, bpp);
+ if (pixel_clk_from_phy == 0) {
+ /* -----------------------------------------------------------
+ * Describing Task phy_cfg_hdmi_pll0_0pt5736 (Clock is input)
+ * -----------------------------------------------------------*/
+
+ /* register CMN_PLL0_VCOCAL_INIT_TMR */
+ write16(0x0084, 0x0064);
+ /* register CMN_PLL0_VCOCAL_ITER_TMR */
+ write16(0x0085, 0x000A);
+ /* register PHY_HDP_CLK_CTL */
+ reg_val = read16(0xC009);
+ reg_val &= 0x00FF;
+ reg_val |= 0x1200;
+ write16(0xC009, reg_val);
+
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ if (inside(pixel_freq_khz, 340000, 600000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x3C);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x06);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 600);
+ } else if (inside(pixel_freq_khz, 170000, 340000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x22);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x07);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 340);
+ } else if (inside(pixel_freq_khz, 85000, 170000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ set_field_value(&cmnda_pll0_ip_div, 0x11);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+ set_field_value(&cmn_ref_clk_dig_div, 0x00);
+ set_field_value(÷r_scaler, 0x07);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 340);
+ } else if (inside(pixel_freq_khz, 42500, 85000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ set_field_value(&cmnda_pll0_ip_div, 0x08);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x132);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 320);
+ } else if (inside(pixel_freq_khz, 25000, 42500)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ set_field_value(&cmnda_pll0_ip_div, 0x05);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 400);
+ } else {
+ ftemp = pixel_freq_khz;
+ debug("Pixel clock frequency (%u) is outside of the supported range\n",
+ ftemp);
+ }
+ break;
+
+ case CLK_RATIO_5_4:
+ if (inside(pixel_freq_khz, 272000, 480000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x30);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x05);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 600);
+ } else if (inside(pixel_freq_khz, 136000, 272000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x1A);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x137);
+ set_field_value(&cmn_ref_clk_dig_div, 0x02);
+ set_field_value(÷r_scaler, 0x04);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 325);
+ } else if (inside(pixel_freq_khz, 68000, 136000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ set_field_value(&cmnda_pll0_ip_div, 0x0D);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x137);
+ set_field_value(&cmn_ref_clk_dig_div, 0x02);
+ set_field_value(÷r_scaler, 0x02);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 325);
+ } else if (inside(pixel_freq_khz, 34000, 68000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ set_field_value(&cmnda_pll0_ip_div, 0x06);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x11E);
+ set_field_value(&cmn_ref_clk_dig_div, 0x02);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 300);
+ } else if (inside(pixel_freq_khz, 25000, 34000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ set_field_value(&cmnda_pll0_ip_div, 0x04);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 400);
+ } else {
+ ftemp = pixel_freq_khz;
+ debug("Pixel clock frequency (%u) is outside of the supported range\n",
+ ftemp);
+ }
+ break;
+ case CLK_RATIO_3_2:
+ if (inside(pixel_freq_khz, 226000, 400000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x28);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x04);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 600);
+ } else if (inside(pixel_freq_khz, 113000, 226000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x16);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x05);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 330);
+ } else if (inside(pixel_freq_khz, 56000, 113000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ set_field_value(&cmnda_pll0_ip_div, 0x0B);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+ set_field_value(&cmn_ref_clk_dig_div, 0x00);
+ set_field_value(÷r_scaler, 0x05);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 330);
+ } else if (inside(pixel_freq_khz, 28000, 56000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ set_field_value(&cmnda_pll0_ip_div, 0x06);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x15A);
+ set_field_value(&cmn_ref_clk_dig_div, 0x02);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 360);
+ } else if (inside(pixel_freq_khz, 25000, 28000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x15A);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 360);
+ } else {
+ ftemp = pixel_freq_khz;
+ debug("Pixel clock frequency (%u) is outside of the supported range\n",
+ ftemp);
+ }
+ break;
+ case CLK_RATIO_2_1:
+ if (inside(pixel_freq_khz, 170000, 300000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x22);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x29A);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x06);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 680);
+ } else if (inside(pixel_freq_khz, 85000, 170000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x11);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+ set_field_value(&cmn_ref_clk_dig_div, 0x00);
+ set_field_value(÷r_scaler, 0x07);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 340);
+ } else if (inside(pixel_freq_khz, 42500, 85000)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ set_field_value(&cmnda_pll0_ip_div, 0x08);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x132);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 320);
+ } else if (inside(pixel_freq_khz, 25000, 42500)) {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ set_field_value(&cmnda_pll0_ip_div, 0x05);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&pll_feedback_divider_total,
+ 400);
+ } else {
+ ftemp = pixel_freq_khz;
+ debug("Pixel clock frequency (%u) is outside of the supported range\n",
+ ftemp);
+ }
+ break;
+ case CLK_RATIO_1_2:
+ if (!(inside(pixel_freq_khz, 594000, 594000))) {
+ ftemp = pixel_freq_khz;
+ debug("Pixel clock frequency (%u) is outside of the supported range\n",
+ ftemp);
+ } else {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ set_field_value(&cmnda_pll0_ip_div, 0x3C);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x06);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 600);
+ }
+ break;
+ case CLK_RATIO_5_8:
+ if (!(inside(pixel_freq_khz, 594000, 594000))) {
+ ftemp = pixel_freq_khz;
+ debug("Pixel clock frequency (%u) is outside of the supported range\n",
+ ftemp);
+ } else {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x3C);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x169);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x06);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 375);
+ }
+ break;
+ case CLK_RATIO_3_4:
+ if (!(inside(pixel_freq_khz, 594000, 594000))) {
+ ftemp = pixel_freq_khz;
+ debug("Pixel clock frequency (%u) is outside of the supported range\n",
+ ftemp);
+ } else {
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ set_field_value(&cmnda_pll0_ip_div, 0x3C);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x1B4);
+ set_field_value(&cmn_ref_clk_dig_div, 0x03);
+ set_field_value(÷r_scaler, 0x06);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 450);
+ }
+ break;
+ }
+ vco_freq =
+ pixel_freq_khz * pll_feedback_divider_total.value /
+ cmnda_pll0_ip_div.value;
+ ftemp = vco_freq;
+ debug("VCO frequency is %u kHz\n", ftemp);
+
+ if (inside(vco_freq, 1700000, 2000000)) {
+ set_field_value(&voltage_to_current_coarse, 0x04);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x09);
+ set_field_value(&ptat_ndac_ctrl, 0x09);
+ switch (pll_feedback_divider_total.value) {
+ case 300:
+ set_field_value(&charge_pump_gain, 0x82);
+ break;
+ case 320:
+ set_field_value(&charge_pump_gain, 0x83);
+ break;
+ case 325:
+ set_field_value(&charge_pump_gain, 0x83);
+ break;
+ case 330:
+ set_field_value(&charge_pump_gain, 0x84);
+ break;
+ case 340:
+ set_field_value(&charge_pump_gain, 0x84);
+ break;
+ case 360:
+ set_field_value(&charge_pump_gain, 0x86);
+ break;
+ case 400:
+ set_field_value(&charge_pump_gain, 0xA2);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else if (inside(vco_freq, 2000000, 2400000)) {
+ set_field_value(&voltage_to_current_coarse, 0x04);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x09);
+ set_field_value(&ptat_ndac_ctrl, 0x09);
+ switch (pll_feedback_divider_total.value) {
+ case 300:
+ set_field_value(&charge_pump_gain, 0x47);
+ break;
+ case 320:
+ set_field_value(&charge_pump_gain, 0x4B);
+ break;
+ case 325:
+ set_field_value(&charge_pump_gain, 0x4C);
+ break;
+ case 330:
+ set_field_value(&charge_pump_gain, 0x80);
+ break;
+ case 340:
+ set_field_value(&charge_pump_gain, 0x81);
+ break;
+ case 360:
+ set_field_value(&charge_pump_gain, 0x82);
+ break;
+ case 400:
+ set_field_value(&charge_pump_gain, 0x84);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else if (inside(vco_freq, 2400000, 2800000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ switch (pll_feedback_divider_total.value) {
+ case 300:
+ set_field_value(&charge_pump_gain, 0x43);
+ break;
+ case 320:
+ set_field_value(&charge_pump_gain, 0x45);
+ break;
+ case 325:
+ set_field_value(&charge_pump_gain, 0x45);
+ break;
+ case 330:
+ set_field_value(&charge_pump_gain, 0x45);
+ break;
+ case 340:
+ set_field_value(&charge_pump_gain, 0x86);
+ break;
+ case 360:
+ set_field_value(&charge_pump_gain, 0x4A);
+ break;
+ case 400:
+ set_field_value(&charge_pump_gain, 0x81);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else if (inside(vco_freq, 2800000, 3400000)) {
+ set_field_value(&voltage_to_current_coarse, 0x06);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ switch (pll_feedback_divider_total.value) {
+ case 300:
+ set_field_value(&charge_pump_gain, 0x3D);
+ break;
+ case 320:
+ set_field_value(&charge_pump_gain, 0x41);
+ break;
+ case 325:
+ set_field_value(&charge_pump_gain, 0x41);
+ break;
+ case 330:
+ set_field_value(&charge_pump_gain, 0x41);
+ break;
+ case 340:
+ set_field_value(&charge_pump_gain, 0x42);
+ break;
+ case 360:
+ set_field_value(&charge_pump_gain, 0x43);
+ break;
+ case 400:
+ set_field_value(&charge_pump_gain, 0x46);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else if (inside(vco_freq, 3400000, 3900000)) {
+ set_field_value(&voltage_to_current_coarse, 0x04);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x07);
+ set_field_value(&ptat_ndac_ctrl, 0x0F);
+ switch (pll_feedback_divider_total.value) {
+ case 375:
+ set_field_value(&charge_pump_gain, 0x41);
+ break;
+ case 600:
+ set_field_value(&charge_pump_gain, 0x82);
+ break;
+ case 680:
+ set_field_value(&charge_pump_gain, 0x85);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else if (inside(vco_freq, 3900000, 4500000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x07);
+ set_field_value(&ptat_ndac_ctrl, 0x0F);
+ switch (pll_feedback_divider_total.value) {
+ case 450:
+ set_field_value(&charge_pump_gain, 0x41);
+ break;
+ case 600:
+ set_field_value(&charge_pump_gain, 0x4B);
+ break;
+ case 680:
+ set_field_value(&charge_pump_gain, 0x82);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else if (inside(vco_freq, 4500000, 5200000)) {
+ set_field_value(&voltage_to_current_coarse, 0x06);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ switch (pll_feedback_divider_total.value) {
+ case 600:
+ set_field_value(&charge_pump_gain, 0x45);
+ break;
+ case 680:
+ set_field_value(&charge_pump_gain, 0x4A);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else if (inside(vco_freq, 5200000, 6000000)) {
+ set_field_value(&voltage_to_current_coarse, 0x07);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ switch (pll_feedback_divider_total.value) {
+ case 600:
+ set_field_value(&charge_pump_gain, 0x42);
+ break;
+ case 680:
+ set_field_value(&charge_pump_gain, 0x45);
+ break;
+ default:
+ debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+ pll_feedback_divider_total.value, ftemp);
+ }
+ } else
+ debug("VCO frequency %u kHz is outside of the supported range\n",
+ ftemp);
+
+ /* register CMN_DIAG_PLL0_INCLK_CTRL */
+ reg_val = set_reg_value(cmnda_pll0_hs_sym_div_sel);
+ reg_val |= set_reg_value(cmnda_pll0_ip_div);
+ write16(0x01CA, reg_val);
+ /* register CMN_DIAG_PLL0_FBL_OVRD */
+ reg_val = set_reg_value(cmnda_pll0_fb_div_low);
+ reg_val |= (1 << 15);
+ write16(0x01C1, reg_val);
+ /* register PHY_PMA_CMN_CTRL1 */
+ reg_val = read16(0xC800);
+ reg_val &= 0xCFFF;
+ reg_val |= set_reg_value(cmn_ref_clk_dig_div);
+ write16(0xC800, reg_val);
+ /* register CMN_CDIAG_REFCLK_CTRL */
+ reg_val = read16(0x0062);
+ reg_val &= 0x8FFF;
+ reg_val |= set_reg_value(divider_scaler);
+ reg_val |= 0x00C0;
+ write16(0x0062, reg_val);
+ /* register CMN_DIAG_HSCLK_SEL */
+ reg_val = read16(0x01E0);
+ reg_val &= 0xFF00;
+ reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0;
+ reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4;
+ write16(0x01E0, reg_val);
+
+ /* register XCVR_DIAG_HSCLK_SEL */
+ for (k = 0; k < num_lanes; k++) {
+ reg_val = read16(0x40E1 | (k << 9));
+ reg_val &= 0xCFFF;
+ reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12;
+ write16(0x40E1 | (k << 9), reg_val);
+ }
+
+ /* register TX_DIAG_TX_CTRL */
+ for (k = 0; k < num_lanes; k++) {
+ reg_val = read16(0x41E0 | (k << 9));
+ reg_val &= 0xFF3F;
+ reg_val |= (tx_subrate.value >> 1) << 6;
+ write16(0x41E0 | (k << 9), reg_val);
+ }
+
+ /* register CMN_PLLSM0_USER_DEF_CTRL */
+ reg_val = set_reg_value(vco_ring_select);
+ write16(0x002F, reg_val);
+ /* register CMN_DIAG_PLL0_OVRD */
+ write16(0x01C2, 0x0000);
+ /* register CMN_DIAG_PLL0_FBH_OVRD */
+ reg_val = set_reg_value(cmnda_pll0_fb_div_high);
+ reg_val |= (1 << 15);
+ write16(0x01C0, reg_val);
+ /* register CMN_DIAG_PLL0_V2I_TUNE */
+ reg_val = set_reg_value(voltage_to_current_coarse);
+ reg_val |= set_reg_value(voltage_to_current);
+ write16(0x01C5, reg_val);
+ /* register CMN_DIAG_PLL0_PTATIS_TUNE1 */
+ reg_val = set_reg_value(pmos_ctrl);
+ reg_val |= set_reg_value(ndac_ctrl);
+ write16(0x01C8, reg_val);
+ /* register CMN_DIAG_PLL0_PTATIS_TUNE2 */
+ reg_val = set_reg_value(ptat_ndac_ctrl);
+ write16(0x01C9, reg_val);
+ /* register CMN_DIAG_PLL0_CP_TUNE */
+ reg_val = set_reg_value(charge_pump_gain);
+ write16(0x01C6, reg_val);
+ /* register CMN_DIAG_PLL0_LF_PROG */
+ write16(0x01C7, 0x0008);
+
+ /* register XCVR_DIAG_PLLDRC_CTRL */
+ for (k = 0; k < num_lanes; k++) {
+ reg_val = read16(0x40E0 | (k << 9));
+ reg_val &= 0xBFFF;
+ write16(0x40E0 | (k << 9), reg_val);
+ }
+
+ } else {
+ /* Describing task phy_cfg_hdmi_pll0_0pt099_ver2
+ (Clock is OUTPUT) */
+ if (inside(pixel_freq_khz, 27000, 27000)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 240);
+ set_field_value(&cmnda_pll0_fb_div_low, 0xBC);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x30);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x26);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x26);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ break;
+ case CLK_RATIO_5_4:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 300);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x0EC);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x03C);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x030);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x030);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ break;
+ case CLK_RATIO_3_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 360);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x11C);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x048);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x03A);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x03A);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ break;
+ case CLK_RATIO_2_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 240);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x0BC);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x030);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ break;
+ default:
+ break;
+ }
+ } else if (inside(pixel_freq_khz, 54000, 54000)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 480);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x17C);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x060);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ break;
+ case CLK_RATIO_5_4:
+ set_field_value(&cmnda_pll0_ip_div, 0x04);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 400);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x050);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x017);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x017);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ break;
+ case CLK_RATIO_3_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x04);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 480);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x17C);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x060);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x01C);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x01C);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ break;
+ case CLK_RATIO_2_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 240);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x0bc);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x030);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ default:
+ break;
+ }
+ } else if (inside(pixel_freq_khz, 74250, 74250)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 660);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x03);
+ break;
+ case CLK_RATIO_5_4:
+ set_field_value(&cmnda_pll0_ip_div, 0x04);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 550);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x017);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x017);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x04);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ break;
+ case CLK_RATIO_3_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x04);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 660);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x01c);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x01c);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ break;
+ case CLK_RATIO_2_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 330);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ default:
+ break;
+ }
+ } else if (inside(pixel_freq_khz, 99000, 99000)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 440);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ break;
+ case CLK_RATIO_5_4:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 275);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x0d8);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x037);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ case CLK_RATIO_3_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 330);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x00d);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x00d);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ case CLK_RATIO_2_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 440);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ default:
+ break;
+ }
+ } else if (inside(pixel_freq_khz, 148500, 148500)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 660);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x02);
+ break;
+ case CLK_RATIO_5_4:
+ set_field_value(&cmnda_pll0_ip_div, 0x04);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 550);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ case CLK_RATIO_3_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 495);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x00d);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x00d);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ case CLK_RATIO_2_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 660);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ default:
+ break;
+ }
+ } else if (inside(pixel_freq_khz, 198000, 198000)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 220);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x0ac);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x02c);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ case CLK_RATIO_5_4:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 550);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ case CLK_RATIO_3_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 330);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x006);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x005);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ case CLK_RATIO_2_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 440);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x008);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x008);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ default:
+ break;
+ }
+ } else if (inside(pixel_freq_khz, 297000, 297000)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 330);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+ set_field_value(&vco_ring_select, 0x00);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ case CLK_RATIO_3_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 495);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x006);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x005);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ case CLK_RATIO_2_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 660);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x008);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x008);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ default:
+ ftemp = pixel_freq_khz;
+ debug("This pixel clock frequency (%u kHz) is not supported with this (%0d-bit) color depth.\n",
+ ftemp, bpp);
+ }
+ } else if (inside(pixel_freq_khz, 594000, 594000)) {
+ switch (clk_ratio) {
+ case CLK_RATIO_1_1:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 660);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ case CLK_RATIO_1_2:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 660);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x02);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x01);
+ break;
+ case CLK_RATIO_5_8:
+ set_field_value(&cmnda_pll0_ip_div, 0x04);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 550);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+ /* does not matter - pixel clock delivered to
+ controller from SoC */
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+ /* does not matter - pixel clock delivered to
+ controller from SoC */
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ case CLK_RATIO_3_4:
+ set_field_value(&cmnda_pll0_ip_div, 0x03);
+ set_field_value(&cmn_ref_clk_dig_div, 0x01);
+ set_field_value(÷r_scaler, 0x01);
+ set_field_value(&pll_feedback_divider_total,
+ 495);
+ set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+ set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+ /* does not matter - pixel clock delivered to
+ controller from SoC */
+ set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+ /* does not matter - pixel clock delivered to
+ controller from SoC */
+ set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+ set_field_value(&vco_ring_select, 0x01);
+ set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+ set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+ set_field_value(&tx_subrate, 0x01);
+ set_field_value(&cmnda_pll0_hs_sym_div_sel,
+ 0x00);
+ break;
+ default:
+ debug("This pixel clock frequency (%d KHz) is not supported with this (%0d-bit) color depth.\n",
+ pixel_freq_khz, bpp);
+ }
+ } else {
+ ftemp = pixel_freq_khz;
+ debug("This pixel clock frequency (%u kHz) is not supported.\n",
+ ftemp);
+ }
+
+ vco_freq =
+ refclk_freq_khz * pll_feedback_divider_total.value /
+ cmnda_pll0_ip_div.value;
+ ftemp = vco_freq;
+ debug("VCO frequency is %u kHz\n", ftemp);
+
+ if (inside(vco_freq, 1980000, 1980000)) {
+ set_field_value(&voltage_to_current_coarse, 0x04);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x09);
+ set_field_value(&ptat_ndac_ctrl, 0x09);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 160);
+ set_field_value(&v2i_code, 5);
+ set_field_value(&vco_cal_code, 183);
+ } else if (inside(vco_freq, 2160000, 2160000)) {
+ set_field_value(&voltage_to_current_coarse, 0x04);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x09);
+ set_field_value(&ptat_ndac_ctrl, 0x09);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 166);
+ set_field_value(&v2i_code, 6);
+ set_field_value(&vco_cal_code, 208);
+ } else if (inside(vco_freq, 2475000, 2475000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 167);
+ set_field_value(&v2i_code, 6);
+ set_field_value(&vco_cal_code, 209);
+ } else if (inside(vco_freq, 2700000, 2700000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ switch (pll_feedback_divider_total.value) {
+ case 300:
+ set_field_value(&charge_pump_gain, 0x042);
+ break;
+ case 400:
+ set_field_value(&charge_pump_gain, 0x04c);
+ break;
+ }
+ set_field_value(&coarse_code, 188);
+ set_field_value(&v2i_code, 6);
+ set_field_value(&vco_cal_code, 225);
+ } else if (inside(vco_freq, 2970000, 2970000)) {
+ set_field_value(&voltage_to_current_coarse, 0x06);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 183);
+ set_field_value(&v2i_code, 6);
+ set_field_value(&vco_cal_code, 225);
+ } else if (inside(vco_freq, 3240000, 3240000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ switch (pll_feedback_divider_total.value) {
+ case 360:
+ set_field_value(&charge_pump_gain, 0x042);
+ break;
+ case 480:
+ set_field_value(&charge_pump_gain, 0x04c);
+ break;
+ }
+ set_field_value(&coarse_code, 203);
+ set_field_value(&v2i_code, 7);
+ set_field_value(&vco_cal_code, 256);
+ } else if (inside(vco_freq, 3712500, 3712500)) {
+ set_field_value(&voltage_to_current_coarse, 0x04);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x07);
+ set_field_value(&ptat_ndac_ctrl, 0x0F);
+ set_field_value(&charge_pump_gain, 0x04c);
+ set_field_value(&coarse_code, 212);
+ set_field_value(&v2i_code, 7);
+ set_field_value(&vco_cal_code, 257);
+ } else if (inside(vco_freq, 3960000, 3960000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x07);
+ set_field_value(&ptat_ndac_ctrl, 0x0F);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 184);
+ set_field_value(&v2i_code, 6);
+ set_field_value(&vco_cal_code, 226);
+ } else if (inside(vco_freq, 4320000, 4320000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x07);
+ set_field_value(&ptat_ndac_ctrl, 0x0F);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 205);
+ set_field_value(&v2i_code, 7);
+ set_field_value(&vco_cal_code, 258);
+ } else if (inside(vco_freq, 4455000, 4455000)) {
+ set_field_value(&voltage_to_current_coarse, 0x05);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x00);
+ set_field_value(&pmos_ctrl, 0x07);
+ set_field_value(&ptat_ndac_ctrl, 0x0F);
+ switch (pll_feedback_divider_total.value) {
+ case 495:
+ set_field_value(&charge_pump_gain, 0x042);
+ break;
+ case 660:
+ set_field_value(&charge_pump_gain, 0x04c);
+ break;
+ }
+ set_field_value(&coarse_code, 219);
+ set_field_value(&v2i_code, 7);
+ set_field_value(&vco_cal_code, 272);
+ } else if (inside(vco_freq, 4950000, 4950000)) {
+ set_field_value(&voltage_to_current_coarse, 0x06);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 213);
+ set_field_value(&v2i_code, 7);
+ set_field_value(&vco_cal_code, 258);
+ } else if (inside(vco_freq, 5940000, 5940000)) {
+ set_field_value(&voltage_to_current_coarse, 0x07);
+ set_field_value(&voltage_to_current, 0x03);
+ set_field_value(&ndac_ctrl, 0x01);
+ set_field_value(&pmos_ctrl, 0x00);
+ set_field_value(&ptat_ndac_ctrl, 0x07);
+ set_field_value(&charge_pump_gain, 0x042);
+ set_field_value(&coarse_code, 244);
+ set_field_value(&v2i_code, 8);
+ set_field_value(&vco_cal_code, 292);
+ } else {
+ ftemp = vco_freq;
+ debug("Current vco_freq (%u kHz) is not supported.\n",
+ ftemp);
+ }
+
+ /* register CMN_PLL0_VCOCAL_INIT_TMR */
+ write16(0x0084, 0x0064);
+ /* register CMN_PLL0_VCOCAL_ITER_TMR */
+ write16(0x0085, 0x000A);
+ /* register PHY_HDP_CLK_CTL */
+ reg_val = read16(0xC009);
+ reg_val &= 0x00FF;
+ reg_val |= 0x2 << 8;
+ reg_val |= 0x1 << 12;
+ write16(0xC009, reg_val);
+ /* register CMN_DIAG_PLL0_INCLK_CTRL */
+ reg_val = set_reg_value(cmnda_pll0_ip_div);
+ reg_val |= set_reg_value(cmnda_pll0_hs_sym_div_sel);
+ write16(0x01CA, reg_val);
+ /* register CMN_DIAG_PLL0_FBH_OVRD */
+ reg_val = set_reg_value(cmnda_pll0_fb_div_high);
+ reg_val |= (1 << 15);
+ write16(0x01C0, reg_val);
+ /* register CMN_DIAG_PLL0_FBL_OVRD */
+ reg_val = set_reg_value(cmnda_pll0_fb_div_low);
+ reg_val |= (1 << 15);
+ write16(0x01C1, reg_val);
+ /* register CMN_DIAG_PLL0_PXL_DIVL */
+ reg_val = set_reg_value(cmnda_pll0_pxdiv_low);
+ write16(0x01CC, reg_val);
+ /* register CMN_DIAG_PLL0_PXL_DIVH */
+ reg_val = set_reg_value(cmnda_pll0_pxdiv_high);
+ reg_val |= (1 << 15);
+ write16(0x01CB, reg_val);
+
+ /* register TX_DIAG_TX_CTRL */
+ for (k = 0; k < num_lanes; k++) {
+ reg_val = read16(0x41E0 | (k << 9));
+ reg_val &= 0xFF3F;
+ reg_val |= (tx_subrate.value >> 1) << 6;
+ write16(0x41E0 | (k << 9), reg_val);
+ }
+
+ /* register PHY_PMA_CMN_CTRL1 */
+ reg_val = read16(0xC800);
+ reg_val &= 0xCFFF;
+ reg_val |= set_reg_value(cmn_ref_clk_dig_div);
+ write16(0xC800, reg_val);
+ /* register CMN_CDIAG_REFCLK_CTRL */
+ reg_val = read16(0x0062);
+ reg_val &= 0x8FFF;
+ reg_val |= set_reg_value(divider_scaler);
+ reg_val |= 0x00C0;
+ write16(0x0062, reg_val);
+ /* register CMN_DIAG_HSCLK_SEL */
+ reg_val = read16(0x01E0);
+ reg_val &= 0xFF00;
+ reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0;
+ reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4;
+ write16(0x01E0, reg_val);
+ /* register CMN_PLLSM0_USER_DEF_CTRL */
+ reg_val = set_reg_value(vco_ring_select);
+ write16(0x002F, reg_val);
+
+ /* register XCVR_DIAG_HSCLK_SEL */
+ for (k = 0; k < num_lanes; k++) {
+ reg_val = read16(0x40E1 | (k << 9));
+ reg_val &= 0xCFFF;
+ reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12;
+ write16(0x40E1 | (k << 9), reg_val);
+ }
+
+ /* register CMN_DIAG_PLL0_OVRD */
+ write16(0x01C2, 0x0000);
+ /* register CMN_DIAG_PLL0_V2I_TUNE */
+ reg_val = set_reg_value(voltage_to_current_coarse);
+ reg_val |= set_reg_value(voltage_to_current);
+ write16(0x01C5, reg_val);
+ /* register CMN_DIAG_PLL0_PTATIS_TUNE1 */
+ reg_val = set_reg_value(pmos_ctrl);
+ reg_val |= set_reg_value(ndac_ctrl);
+ write16(0x01C8, reg_val);
+ /* register CMN_DIAG_PLL0_PTATIS_TUNE2 */
+ reg_val = set_reg_value(ptat_ndac_ctrl);
+ write16(0x01C9, reg_val);
+ /* register CMN_PLL0_VCOCAL_START */
+ reg_val = read16(0x0081);
+ reg_val &= 0xFE00;
+ reg_val |= set_reg_value(vco_cal_code);
+ write16(0x0081, reg_val);
+ /* register CMN_DIAG_PLL0_CP_TUNE */
+ reg_val = set_reg_value(charge_pump_gain);
+ write16(0x01C6, reg_val);
+ /* register CMN_DIAG_PLL0_LF_PROG */
+ write16(0x01C7, 0x0008);
+
+ /* register XCVR_DIAG_PLLDRC_CTRL */
+ for (k = 0; k < num_lanes; k++) {
+ reg_val = read16(0x40E0 | (k << 9));
+ reg_val &= 0xBFFF;
+ write16(0x40E0 | (k << 9), reg_val);
+ }
+ }
+
+ /* Back to task phy_cfg_hdp */
+
+ /* register PHY_PMA_CMN_CTRL1 */
+ reg_val = read16(0xC800);
+ reg_val &= 0xFF8F;
+ /* for differential clock on the refclk_p and refclk_m
+ * off chip pins: PHY_PMA_CMN_CTRL1[6:4]=3'b000 */
+ reg_val |= 0x0000;
+ write16(0xC800, reg_val);
+
+ /* register CMN_DIAG_ACYA */
+ write16(0x01FF, 0x0100);
+
+ if (phy_reset_workaround) {
+ /* register PHY_ISO_CMN_CTRL */
+ write16(0xC010, 0x0001); /* Deassert PHY reset */
+ /* register PHY_PMA_ISO_CMN_CTRL */
+ write16(0xC810, 0x0003);
+ for (k = 0; k < num_lanes; k++) {
+ /* register XCVR_PSM_RCTRL */
+ write16(0x4001 | (k << 9), 0xFEFC);
+ }
+ /* register PHY_PMA_ISO_CMN_CTRL
+ * Assert cmn_macro_pwr_en*/
+ write16(0xC810, 0x0013);
+
+ /* PHY_PMA_ISO_CMN_CTRL
+ * wait for cmn_macro_pwr_en_ack*/
+ while (!(read16(0xC810) & (1 << 5)))
+ ;
+
+ /* PHY_PMA_CMN_CTRL1 wait for cmn_ready */
+ while (!(read16(0xC800) & (1 << 0)))
+ ;
+ } else {
+ for (k = 0; k < num_lanes; k++) {
+ /* register XCVR_PSM_RCTRL */
+ write16(0x4001 | (k << 9), 0xBEFC);
+ }
+ }
+ for (k = 0; k < num_lanes; k++) {
+ /* register TX_PSC_A0 */
+ write16(0x4100 | (k << 9), 0x6791);
+ /* register TX_PSC_A1 */
+ write16(0x4101 | (k << 9), 0x6790);
+ /* register TX_PSC_A2 */
+ write16(0x4102 | (k << 9), 0x0090);
+ /* register TX_PSC_A3 */
+ write16(0x4103 | (k << 9), 0x0090);
+ /* register RX_PSC_CAL */
+ reg_val = read16(0x8006 | (k << 9));
+ reg_val &= 0xFFBB;
+ write16(0x8006 | (k << 9), reg_val);
+ reg_val = read16(0x8000 | (k << 9));
+ reg_val &= 0xFFBB;
+ write16(0x8000 | (k << 9), reg_val);
+ }
+
+ /* End of task phy_cfg_hdp */
+ /* register PHY_HDP_MODE_CTL */
+ write16(0xC008, 0x0004);
+
+ aux_cfg_t28hpc();
+ return character_freq_khz;
+}
+
+int hdmi_tx_t28hpc_power_config_seq(int num_lanes)
+{
+ unsigned char k;
+
+ /* Configure the power state.
+ * register TX_DIAG_ACYA */
+ for (k = 0; k < num_lanes; k++) {
+ /* register XCVR_PSM_CAL_TMR */
+ write16(0x41FF | (k << 9), 0x0001);
+ }
+
+ /* register PHY_DP_MODE_CTL */
+ while (!(read16(0xC008) & (1 << 6)))
+ ;
+
+ /* PHY_DP_MODE_CTL */
+ write16(0xC008, (((0x0F << num_lanes) & 0x0F) << 12) | 0x0101);
+
+ /* PHY_DP_MODE_CTL */
+ while (!(read16(0xC008) & (1 << 4)))
+ ;
+
+ return 0;
+}
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_t28hpc_hdmitx.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_T28HPC_HDMITX_H_
+#define API_AFE_T28HPC_HDMITX_H_
+
+#ifndef __UBOOT__
+#include <assert.h>
+#include <stdint.h>
+#else
+#include <common.h>
+#endif
+#include "vic_table.h"
+#include "API_AFE.h"
+#include "externs.h"
+
+int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp,
+ VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy);
+int hdmi_tx_t28hpc_power_config_seq(int num_lanes);
+
+#endif
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AVI.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_AVI.h"
+#include "API_Infoframe.h"
+
+CDN_API_STATUS cdn_api_set_avi(VIC_MODES vic_mode,
+ VIC_PXL_ENCODING_FORMAT color_mode,
+ BT_TYPE itu_ver)
+{
+ unsigned int active_slot = vic_table[vic_mode][H_BLANK];
+ unsigned int line_width = vic_table[vic_mode][H_TOTAL];
+ unsigned int hactive = line_width - active_slot + 1;
+ unsigned int vactive = vic_table[vic_mode][V_ACTIVE] + 1;
+
+ unsigned int hactive_l = hactive - 256 * ((unsigned int)hactive / 256);
+ unsigned int hactive_h = hactive / 256;
+ unsigned int vactive_l = vactive - 256 * ((unsigned int)vactive / 256);
+ unsigned int vactive_h = vactive / 256;
+
+ /* unsigned int packet; */
+
+ unsigned int packet_type = 0x82;
+ unsigned int packet_version = 0x2;
+ unsigned int packet_len = 0xd;
+ unsigned int packet_y = 0;
+ unsigned int packet_c = 0;
+ unsigned int packet_r = 0;
+ unsigned int packet_vic = 0;
+ unsigned int packet_pr = 0;
+ unsigned int packet_buf[18 / sizeof(unsigned int)];
+ unsigned char *packet = (unsigned char *)&packet_buf[0];
+ unsigned int packet_hb0 = 0;
+ unsigned int packet_hb1 = 0;
+ unsigned int packet_hb2 = 0;
+ unsigned int packet_pb0 = 0;
+ unsigned int packet_pb1 = 0;
+ unsigned int packet_pb2 = 0;
+ unsigned int packet_pb3 = 0;
+ unsigned int packet_pb4 = 0;
+ unsigned int packet_pb5 = 0;
+ unsigned int packet_pb6 = 0;
+ unsigned int packet_pb7 = 0;
+ unsigned int packet_pb8 = 0;
+ unsigned int packet_pb9 = 0;
+ unsigned int packet_pb10 = 0;
+ unsigned int packet_pb11 = 0;
+ unsigned int packet_pb12 = 0;
+ unsigned int packet_pb13 = 0;
+ unsigned int pb1_13_chksum = 0;
+ unsigned int packet_chksum = 0;
+
+ if (color_mode == PXL_RGB)
+ packet_y = 0;
+ else if (color_mode == YCBCR_4_4_4)
+ packet_y = 2;
+ else if (color_mode == YCBCR_4_2_2)
+ packet_y = 1;
+ else if (color_mode == YCBCR_4_2_0)
+ packet_y = 3;
+
+ /* Colorimetry: Nodata=0 IT601=1 ITU709=2 */
+ if (itu_ver == BT_601)
+ packet_c = 1;
+ else if (itu_ver == BT_709)
+ packet_c = 2;
+ else
+ packet_c = 0;
+
+ unsigned int packet_a0 = 1;
+ unsigned int packet_b = 0;
+ unsigned int packet_s = 0;
+ unsigned int packet_sc = 0; /* Picture Scaling */
+
+ /* Active Format Aspec Ratio: Same As Picture = 0x8 4:3(Center)=0x9
+ 16:9=0xA 14:9=0xB */
+ packet_r = vic_table[vic_mode][VIC_R3_0];
+ /* Aspect Ratio: Nodata=0 4:3=1 16:9=2 */
+ unsigned int packet_m = 0;
+ /* Quantization Range Default=0 Limited Range=0x1 FullRange=0x2
+ Reserved 0x3 */
+ unsigned int packet_q = 0;
+ /* Quantization Range 0=Limited Range FullRange=0x1 Reserved 0x3/2 */
+ unsigned int packet_yq = 0;
+ /* Extended Colorimetry xvYCC601=0x0 xvYCC709=1 All other Reserved */
+ unsigned int packet_ec = 0;
+ /*IT content nodata=0 ITcontent=1 */
+ unsigned int packet_it = 0;
+ /* Video Code (CEA) */
+ packet_vic = vic_table[vic_mode][VIC];
+ /* Pixel Repetition 0 ... 9 (1-10) */
+ packet_pr = vic_table[vic_mode][VIC_PR];
+ /* Content Type */
+ unsigned int packet_cn = 0;
+
+ packet_hb0 = packet_type;
+ packet_hb1 = packet_version;
+ packet_hb2 = packet_len;
+
+ packet_pb1 = 32 * packet_y + 16 * packet_a0 + 4 * packet_b + packet_s;
+ packet_pb2 = 64 * packet_c + 16 * packet_m + packet_r;
+ packet_pb3 =
+ 128 * packet_it + 16 * packet_ec + 4 * packet_q + packet_sc;
+ packet_pb4 = packet_vic;
+ packet_pb5 = 64 * packet_yq + 16 * packet_cn + packet_pr;
+ packet_pb6 = 0;
+ packet_pb7 = 0;
+ packet_pb8 = vactive_l;
+ packet_pb9 = vactive_h;
+ packet_pb10 = 0;
+ packet_pb11 = 0;
+ packet_pb12 = hactive_l;
+ packet_pb13 = hactive_h;
+
+ pb1_13_chksum =
+ (packet_hb0 + packet_hb1 + packet_hb2 + packet_pb1 +
+ packet_pb2 + packet_pb3 + packet_pb4 + packet_pb5 +
+ packet_pb6 + packet_pb7 + packet_pb8 + packet_pb9 +
+ packet_pb10 + packet_pb11 + packet_pb12 + packet_pb13);
+ packet_chksum =
+ 256 - (pb1_13_chksum -
+ 256 * ((unsigned int)pb1_13_chksum / 256));
+ packet_pb0 = packet_chksum;
+
+ packet[0] = 0;
+ packet[1] = packet_hb0;
+ packet[2] = packet_hb1;
+ packet[3] = packet_hb2;
+ packet[4] = packet_pb0;
+ packet[5] = packet_pb1;
+ packet[6] = packet_pb2;
+ packet[7] = packet_pb3;
+ packet[8] = packet_pb4;
+ packet[9] = packet_pb5;
+ packet[10] = packet_pb6;
+ packet[11] = packet_pb7;
+ packet[12] = packet_pb8;
+ packet[13] = packet_pb9;
+ packet[14] = packet_pb10;
+ packet[15] = packet_pb11;
+ packet[16] = packet_pb12;
+ packet[17] = packet_pb13;
+
+ cdn_api_infoframeset(0, packet_len,
+ (unsigned int *)&packet[0], packet_type);
+
+ return CDN_OK;
+} /* End API */
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AVI.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AVI_H_
+#define API_AVI_H_
+
+#include "vic_table.h"
+#include "API_General.h"
+
+CDN_API_STATUS cdn_api_set_avi(
+ VIC_MODES vic_mode,
+ VIC_PXL_ENCODING_FORMAT color_mode,
+ BT_TYPE itu_ver);
+
+#endif /*API_AVI_H_ */
+
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_HDMITX.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_HDMITX.h"
+#include "util.h"
+#include "opcodes.h"
+#ifndef __UBOOT__
+#include "string.h"
+#include "stdio.h"
+#endif
+#include "mhl_hdtx_top.h"
+#include "source_phy.h"
+#include "address.h"
+#include "source_car.h"
+#include "source_vif.h"
+#include "general_handler.h"
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out)
+{
+ internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_READ,
+ CDN_BUS_TYPE_APB, 3,
+ 1, data_in->slave,
+ 1, data_in->offset,
+ 2, data_in->len
+ );
+ internal_readmsg(5,
+ 1, &data_out->status,
+ 1, &data_out->slave,
+ 1, &data_out->offset,
+ 2, &data_out->len,
+ 0, &data_out->buff
+ );
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out)
+{
+ internal_block_function(CDN_API_HDMITX_DDC_READ(data_in, data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out)
+{
+ printf("foo: %x\n", data_in->buff[0]);
+ internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE,
+ CDN_BUS_TYPE_APB, 4,
+ 1, data_in->slave,
+ 1, data_in->offset,
+ 2, data_in->len,
+ -data_in->len, data_in->buff
+ );
+ internal_readmsg(4,
+ 1, &data_out->status,
+ 1, &data_out->slave,
+ 1, &data_out->offset,
+ 2, &data_out->len
+ );
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out)
+{
+ internal_block_function(CDN_API_HDMITX_DDC_WRITE(data_in, data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out)
+{
+ internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_UPDATE_READ,
+ CDN_BUS_TYPE_APB, 0);
+ internal_readmsg(2,
+ 1, &data_out->status,
+ 0, &data_out->buff
+ );
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA
+ *data_out)
+{
+ internal_block_function(CDN_API_HDMITX_DDC_UPDATE_READ(data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block,
+ unsigned char segment,
+ HDMITX_TRANS_DATA *data_out)
+{
+ internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID,
+ CDN_BUS_TYPE_APB, 2,
+ 1, block,
+ 1, segment
+ );
+ internal_readmsg(5,
+ 1, &data_out->status,
+ 1, &data_out->slave,
+ 1, &data_out->offset,
+ 2, &data_out->len,
+ 0, &data_out->buff
+ );
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block,
+ unsigned char segment,
+ HDMITX_TRANS_DATA *data_out)
+{
+ internal_block_function(CDN_API_HDMITX_READ_EDID(block, segment,
+ data_out));
+}
+
+CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+ unsigned int character_rate)
+{
+ CDN_API_STATUS ret;
+ GENERAL_READ_REGISTER_RESPONSE resp;
+ HDMITX_TRANS_DATA data_in;
+ HDMITX_TRANS_DATA data_out;
+ unsigned char buff = 1;
+
+ /*enable/disable scrambler; */
+ if (protocol == HDMI_TX_MODE_HDMI_2_0) {
+ if (character_rate > 340000)
+ buff = 3; /*enable scrambling + TMDS_Bit_Clock_Ratio */
+ else
+ buff = 1; /*enable scrambling */
+ } else {
+ buff = 0; /*disable scrambling */
+ }
+
+ data_in.buff = &buff;
+ data_in.len = 1;
+ data_in.slave = 0x54;
+ data_in.offset = 0x20; /*TMDS config */
+#if 1
+ if (protocol == HDMI_TX_MODE_HDMI_2_0)
+ ret = CDN_API_HDMITX_DDC_WRITE_blocking(&data_in, &data_out);
+
+#endif
+ ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ &resp);
+
+ /*remove data enable */
+ resp.val = resp.val & (~(F_DATA_EN(1)));
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ resp.val);
+
+ if (protocol == HDMI_TX_MODE_HDMI_2_0) {
+ if (character_rate > 3400000) {
+ /* Set TMDS clock ratio */
+ ret = cdn_api_general_write_register_blocking
+ (ADDR_SOURCE_MHL_HD +
+ (HDTX_CLOCK_REG_0 << 2),
+ F_DATA_REGISTER_VAL_0(0x00000));
+ ret = cdn_api_general_write_register_blocking
+ (ADDR_SOURCE_MHL_HD +
+ (HDTX_CLOCK_REG_1 << 2),
+ F_DATA_REGISTER_VAL_1(0xFFFFF));
+ }
+ }
+
+ /*set hdmi mode and preemble mode */
+ resp.val = resp.val & (~(F_HDMI_MODE(3)));
+ resp.val = resp.val & (~(F_HDMI2_PREAMBLE_EN(1)));
+
+ resp.val = (resp.val) | (F_HDMI_MODE(protocol)) |
+ (F_HDMI2_PREAMBLE_EN(1));
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ resp.val);
+
+ /*data enable */
+ resp.val |= F_DATA_EN(1);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ resp.val);
+
+ return ret;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void)
+{
+ CDN_API_STATUS ret;
+
+ /*init phy and CAR and HDMI TX */
+/* ret = cdn_api_general_write_register_blocking
+ (ADDR_SOURCD_PHY + (LANES_CONFIG<<2),
+ F_SOURCE_PHY_LANE0_SWAP(0) |
+ F_SOURCE_PHY_LANE1_SWAP(1) |
+ F_SOURCE_PHY_LANE2_SWAP(2) |
+ F_SOURCE_PHY_LANE3_SWAP(3) |
+ F_SOURCE_PHY_COMB_BYPASS(0) |
+ F_SOURCE_PHY_20_10(1)); */
+
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCD_PHY +
+ (PHY_DATA_SEL << 2),
+ F_SOURCE_PHY_MHDP_SEL(1));
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_HPD << 2),
+ F_HPD_VALID_WIDTH(4) |
+ F_HPD_GLITCH_WIDTH(0));
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ F_HDMI_MODE(1) |
+ F_AUTO_MODE(0) |
+ F_GCP_EN(1) |
+ F_DATA_EN(1) |
+ F_CLEAR_AVMUTE(1) |
+ F_HDMI2_PREAMBLE_EN(1) |
+ F_HDMI2_CTRL_IL_MODE(1) |
+ F_PIC_3D(0XF) |
+ F_BCH_EN(1));
+ /* open CARS */
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+ (SOURCE_PHY_CAR << 2),
+ 0xF);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+ (SOURCE_HDTX_CAR << 2),
+ 0xFF);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+ (SOURCE_PKT_CAR << 2),
+ 0xF);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+ (SOURCE_AIF_CAR << 2),
+ 0xF);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+ (SOURCE_CIPHER_CAR << 2),
+ 0xF);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+ (SOURCE_CRYPTO_CAR << 2),
+ 0xF);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+ (SOURCE_CEC_CAR << 2), 3);
+
+ /*init vif */
+ /*ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF
+ +(HSYNC2VSYNC_POL_CTRL<<2), F_HPOL(0) | F_VPOL(0)); */
+
+ return ret;
+}
+
+
+CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode, int bpp,
+ VIC_PXL_ENCODING_FORMAT format)
+{
+ CDN_API_STATUS ret;
+ GENERAL_READ_REGISTER_RESPONSE resp;
+ unsigned int vsync_lines = vic_table[vicMode][VSYNC];
+ unsigned int eof_lines = vic_table[vicMode][TYPE_EOF];
+ unsigned int sof_lines = vic_table[vicMode][SOF];
+ unsigned int hblank = vic_table[vicMode][H_BLANK];
+ unsigned int hactive = vic_table[vicMode][H_TOTAL] - hblank;
+ unsigned int vblank = vsync_lines + eof_lines + sof_lines;
+ unsigned int vactive = vic_table[vicMode][V_TOTAL] - vblank;
+ unsigned int hfront = vic_table[vicMode][FRONT_PORCH];
+ unsigned int hback = vic_table[vicMode][BACK_PORCH];
+ unsigned int vfront = eof_lines;
+ unsigned int hsync = hblank - hfront - hback;
+ unsigned int vsync = vsync_lines;
+ unsigned int vback = sof_lines;
+ unsigned int v_h_polarity = ((vic_table[vicMode][HSYNC_POL] ==
+ ACTIVE_LOW) ? 0 : 1) +
+ ((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2);
+
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (SCHEDULER_H_SIZE << 2),
+ (hactive << 16) + hblank);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (SCHEDULER_V_SIZE << 2),
+ (vactive << 16) + vblank);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_SIGNAL_FRONT_WIDTH
+ << 2),
+ (vfront << 16) + hfront);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_SIGNAL_SYNC_WIDTH
+ << 2),
+ (vsync << 16) + hsync);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_SIGNAL_BACK_WIDTH
+ << 2),
+ (vback << 16) + hback);
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF +
+ (HSYNC2VSYNC_POL_CTRL
+ << 2),
+ v_h_polarity);
+
+ /* Data Enable is 1 */
+
+ /*Reset Data Enable */
+ cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2), &resp);
+
+ /*reset data enable */
+ resp.val = resp.val & (~(F_DATA_EN(1)));
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ resp.val);
+
+ /*set bpp */
+ resp.val = resp.val & (~(F_VIF_DATA_WIDTH(3)));
+ switch (bpp) {
+ case 8:
+ resp.val = resp.val | (F_VIF_DATA_WIDTH(0));
+ break;
+
+ case 10:
+ resp.val = resp.val | (F_VIF_DATA_WIDTH(1));
+ break;
+
+ case 12:
+ resp.val = resp.val | (F_VIF_DATA_WIDTH(2));
+ break;
+
+ case 16:
+ resp.val = resp.val | (F_VIF_DATA_WIDTH(3));
+ break;
+ }
+
+ /*select color encoding */
+ resp.val = resp.val & (~(F_HDMI_ENCODING(3)));
+ switch (format) {
+ case PXL_RGB:
+
+ resp.val = resp.val | (F_HDMI_ENCODING(0));
+ break;
+
+ case YCBCR_4_4_4:
+ resp.val = resp.val | (F_HDMI_ENCODING(2));
+ break;
+
+ case YCBCR_4_2_2:
+ resp.val = resp.val | (F_HDMI_ENCODING(1));
+ break;
+
+ case YCBCR_4_2_0:
+ resp.val = resp.val | (F_HDMI_ENCODING(3));
+ break;
+ case Y_ONLY:
+ /*not exist in hdmi */
+ break;
+ }
+
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ resp.val);
+
+ /*set data enable */
+ resp.val = resp.val | (F_DATA_EN(1));
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ resp.val);
+
+ return ret;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force,
+ unsigned char val)
+{
+ unsigned int valToWrite = F_COLOR_DEPTH_VAL(val) |
+ F_COLOR_DEPTH_FORCE(force);
+
+ return cdn_api_general_write_register_blocking
+ (ADDR_SOURCE_MHL_HD +
+ (GCP_FORCE_COLOR_DEPTH_CODING << 2),
+ valToWrite);
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events)
+{
+ CDN_API_STATUS ret;
+
+ if (!state.running) {
+ if (!internal_apb_available())
+ return CDN_BSY;
+
+ internal_tx_mkfullmsg(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS, 0);
+ state.rxenable = 1;
+ state.bus_type = CDN_BUS_TYPE_APB;
+
+ return CDN_STARTED;
+ }
+
+ INTERNAL_PROCESS_MESSAGES;
+
+ ret = internal_test_rx_head(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS);
+
+ if (ret != CDN_OK)
+ return ret;
+
+ internal_readmsg(1, 4, events);
+
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events)
+{
+ internal_block_function(CDN_API_HDMITX_ReadEvents(events));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts)
+{
+ CDN_API_STATUS ret;
+
+ if (!state.running) {
+ if (!internal_apb_available())
+ return CDN_BSY;
+
+ /*
+ * General Module is used here for obtaining HPD State because
+ * HDMI TX Module is inactive in stand-by mode, thus cannot
+ * return it.
+ */
+ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL,
+ GENERAL_GET_HPD_STATE, 0);
+ state.rxenable = 1;
+ state.bus_type = CDN_BUS_TYPE_APB;
+
+ return CDN_STARTED;
+ }
+
+ INTERNAL_PROCESS_MESSAGES;
+
+ ret = internal_test_rx_head(MB_MODULE_ID_GENERAL,
+ GENERAL_GET_HPD_STATE);
+
+ if (ret != CDN_OK)
+ return ret;
+
+ internal_readmsg(1, 1, hpd_sts);
+
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts)
+{
+ internal_block_function(CDN_API_HDMITX_GetHpdStatus(hpd_sts));
+}
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_HDMITX.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _API_HDMITX_H_
+# define _API_HDMITX_H_
+
+# include "API_General.h"
+# include "hdmi.h"
+# include "vic_table.h"
+
+/**
+ * \addtogroup HDMI_TX_API
+ * \{
+ */
+
+# define HDMI_TX_EVENT_CODE_HPD_HIGH 0x01
+# define HDMI_TX_EVENT_CODE_HPD_LOW 0x02
+# define HDMI_TX_EVENT_CODE_HPD_STATE_LOW 0x00
+# define HDMI_TX_EVENT_CODE_HPD_STATE_HIGH 0x08
+
+typedef struct {
+ /** if used to return data, this pointer is set (instead of being a
+ * destination to copy data to
+ */
+ unsigned char *buff;
+ HDMI_I2C_STATUS status;
+ unsigned short len;
+ unsigned char slave;
+ unsigned char offset;
+} HDMITX_TRANS_DATA;
+
+
+typedef enum {
+ HDMI_TX_MODE_DVI,
+ HDMI_TX_MODE_HDMI_1_4,
+ HDMI_TX_MODE_HDMI_2_0,
+} HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE;
+
+/**
+ * \brief I2C read transaction
+ * \param [in] data_in - fields used: len, slave, offset
+ * \param [out] data_out - fields used: all
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C write transaction
+ * \param [in] data_in - fields used: len, slave, offset, buff
+ * \param [out] data_out - fields used: status, len, slave, offset
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in,
+ HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C update read
+ * \param [out] data_out - fields used: status, buff
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS
+CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C read edid
+ * \param [in] block - EDID block
+ * \pram [in] segment - EDID segment
+ * \param [out] data_out - fields used: status, buff, slave (as block),
+ * offset (as segment), len
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block,
+ unsigned char segment,
+ HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block,
+ unsigned char segment,
+ HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief set hdmi protocol type (DVI,1.x,2.x) (send scrambler command over
+ * scdc and set bits in controller)
+ * \param [in] protocol - type
+ * \returns status
+ */
+/*CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+ float character_rate);*/
+CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+ unsigned int character_rate);
+/**
+ * \brief init hdmi registers
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void);
+
+/**
+ * \brief change to vid id vicMode
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode,
+ int bpp,
+ VIC_PXL_ENCODING_FORMAT format);
+
+/**
+ * \brief option to force color depth in the gcp or not force (HW mode)
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force,
+ unsigned char val);
+
+/**
+ * \brief send HDMI_TX_TX_READ_EVENTS command
+ */
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events);
+
+/**
+ * blocking version of #CDN_API_HDMITX_ReadEvents
+ */
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events);
+
+/**
+ * \brief get current HPD status
+ */
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts);
+
+/**
+ * \brief blocking version of #CDN_API_HDMITX_GetHpdStatus
+ */
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts);
+
+#endif
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_Infoframe.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_Infoframe.h"
+#include "address.h"
+#include "source_pif.h"
+#include "externs.h"
+#ifndef __UBOOT__
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#else
+#include <common.h>
+#include <asm/io.h>
+#endif
+#include "util.h"
+
+#define BANK_OFFSET 0x0
+
+/* Redefined because of compiler warnings about 32 bit shift left */
+#ifdef F_DATA_WR
+#undef F_DATA_WR
+#define F_DATA_WR(a_) ((uint32_t)(a_))
+#endif
+
+static CDN_API_STATUS infoframeSet(unsigned char entry_id,
+ unsigned char packet_len,
+ unsigned int *packet,
+ unsigned char packet_type,
+ unsigned char active_idle)
+{
+ unsigned int idx;
+ unsigned int activeIdleBit = (0 == active_idle) ? 0 : 0x20000;
+ /*invalidate entry */
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_PKT_ALLOC_REG << 2),
+ activeIdleBit | F_PKT_ALLOC_ADDRESS(entry_id)))
+ return CDN_ERR;
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+ F_PKT_ALLOC_WR_EN(1)))
+ return CDN_ERR;
+
+ /*flush fifo 1 */
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_FIFO1_FLUSH << 2),
+ F_FIFO1_FLUSH(1)))
+ return CDN_ERR;
+
+ /*write packet into memory */
+ for (idx = 0; idx < packet_len; idx++)
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_DATA_WR << 2),
+ F_DATA_WR(packet[idx])))
+ return CDN_ERR;
+
+ /*write entry id */
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_WR_ADDR << 2),
+ F_WR_ADDR(entry_id)))
+ return CDN_ERR;
+
+ /*write request */
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_WR_REQ << 2),
+ F_HOST_WR(1)))
+ return CDN_ERR;
+
+ /*update entry */
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_PKT_ALLOC_REG << 2),
+ activeIdleBit | F_TYPE_VALID(1) |
+ F_PACKET_TYPE(packet_type) |
+ F_PKT_ALLOC_ADDRESS(entry_id)))
+ return CDN_ERR;
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+ F_PKT_ALLOC_WR_EN(1)))
+ return CDN_ERR;
+
+ return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id,
+ unsigned char packet_len,
+ unsigned int *packet,
+ unsigned char packet_type)
+{
+ return infoframeSet(entry_id, packet_len, packet, packet_type, 1);
+}
+
+CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id,
+ unsigned char packet_len,
+ unsigned int *packet,
+ unsigned char packet_type)
+{
+ return infoframeSet(entry_id, packet_len, packet, packet_type, 0);
+}
+
+CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id)
+{
+ /*invalidate entry */
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_PKT_ALLOC_REG << 2),
+ 0x20000 | F_PKT_ALLOC_ADDRESS(entry_id)))
+ return CDN_ERR;
+ if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+ (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+ F_PKT_ALLOC_WR_EN(1)))
+ return CDN_ERR;
+
+ return CDN_OK;
+}
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_Infoframe.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_INFOFRAME_H
+# define API_INFOFRAME_H
+
+/**
+ * \addtogroup INFO_FRAME_API
+ * \{
+ */
+
+# include "API_General.h"
+
+CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id,
+ unsigned char packet_len,
+ unsigned int *packet,
+ unsigned char packet_type);
+CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id,
+ unsigned char packet_len,
+ unsigned int *packet,
+ unsigned char packet_type);
+CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id);
+
+#endif
+
-obj-y += API_General.o util.o test_base_sw.o
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += API_General.o util.o test_base_sw.o
+
+obj-$(CONFIG_VIDEO_IMX8_HDMI) += \
+ API_General.o \
+ test_base_sw.o \
+ API_AVI.o \
+ API_Infoframe.o \
+ util.o \
+ vic_table.o \
+ edid_parser.o \
+ API_AFE.o \
+ API_HDMITX.o \
+ API_AFE_t28hpc_hdmitx.o
+
+# common objects
+#obj-y += \
+# API_General.o API_AVI.o API_Infoframe.o \
+# util.o vic_table.o test_base_sw.o \
+# avgen_drv.o edid_parser.o \
+# API_AFE.o
+
+#DP objects
+# API_DPTX.o \
+# API_AFE_mcu2_dp.o\
+# mhdp_firmware.o
+
+#hdmi objects
+#obj-y += \
+# API_HDMITX.o \
+# API_HDCP.o \
+# API_AFE_t28hpc_hdmitx.o
+#
+
+# USE for QM
+# blob/API_AFE_mcu1_dp.o
+# blob/API_AFE_ss28fdsoi_kiran_hdmitx.o
+# blob/ss28fdsoi_hdmitx_table.o
+# blob/hdmitx_firmware.o
+# blob/mhdp_firmware.o
+
+# Use for mscale
+# API_AFE_mcu2_dp.o ()
+# API_AFE_t28hpc_hdmitx.c
+#
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * avgen.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef AVGEN_H_
+# define AVGEN_H_
+
+
+/* register HDMIPOL */
+# define HDMIPOL 0
+# define F_HDMI_V_H_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0)
+# define F_HDMI_V_H_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+# define F_HDMI_BITWIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
+# define F_HDMI_BITWIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+
+/* register HDMI_FRONT_PORCHE_L */
+# define HDMI_FRONT_PORCHE_L 1
+# define F_HDMI_FRONT_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRONT_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDFP */
+# define HDFP 2
+# define F_HDMI_FRONT_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRONT_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDBP */
+# define HDBP 3
+# define F_HDMI_BACK_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_BACK_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_BACK_PORCHE_H */
+# define HDMI_BACK_PORCHE_H 4
+# define F_HDMI_BACK_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_BACK_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDAS */
+# define HDAS 5
+# define F_HDMI_ACTIVE_SLOT_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_ACTIVE_SLOT_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_ACTIVE_SLOT_H */
+# define HDMI_ACTIVE_SLOT_H 6
+# define F_HDMI_ACTIVE_SLOT_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_ACTIVE_SLOT_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDFL */
+# define HDFL 7
+# define F_HDMI_FRAME_LINES_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRAME_LINES_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_FRAME_LINES_H */
+# define HDMI_FRAME_LINES_H 8
+# define F_HDMI_FRAME_LINES_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRAME_LINES_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDLW */
+# define HDLW 9
+# define F_HDMI_LINE_WIDTH_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_LINE_WIDTH_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_LINE_WIDTH_H */
+# define HDMI_LINE_WIDTH_H 10
+# define F_HDMI_LINE_WIDTH_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_LINE_WIDTH_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDVL */
+# define HDVL 11
+# define F_HDMI_VSYNC_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_VSYNC_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDEL */
+# define HDEL 12
+# define F_HDMI_EOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_EOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDSL */
+# define HDSL 13
+# define F_HDMI_SOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_SOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDCFUPDT */
+# define HDCFUPDT 14
+# define F_HDMI_CODE_FORMAT_UPDT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_HDMI_CODE_FORMAT_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register HDCF */
+# define HDCF 15
+# define F_HDMI_CODE_FORMAT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_HDMI_CODE_FORMAT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register HDASPACE */
+# define HDASPACE 16
+# define F_HDASPACE(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDASPACE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_3D_MODE */
+# define HDMI_3D_MODE 17
+# define F_HDMI_3D_MODE(x) (((x) & ((1 << 3) - 1)) << 0)
+# define F_HDMI_3D_MODE_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+/* register PTRNGENR */
+# define PTRNGENR 18
+# define F_PTRNGENR_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENR_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENR_H */
+# define PTRNGENR_H 19
+# define F_PTRNGENR_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENR_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENG */
+# define PTRNGENG 20
+# define F_PTRNGENG_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENG_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNEGENG_H */
+# define PTRNEGENG_H 21
+# define F_PTRNGENG_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENG_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENB */
+# define PTRNGENB 22
+# define F_PTRNGENB_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENB_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRGENB */
+# define PTRGENB 23
+# define F_PTRNGENB_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENB_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENFF */
+# define PTRNGENFF 30
+# define F_PTRNGENIP(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_PTRNGENIP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register PGENCTRL */
+# define PGENCTRL 32
+# define F_PGENCF(x) (((x) & ((1 << 6) - 1)) << 1)
+# define F_PGENCF_RD(x) (((x) & (((1 << 6) - 1) << 1)) >> 1)
+# define F_PTRNGENSTRT(x) (((x) & ((1 << 1) - 1)) << 7)
+# define F_PTRNGENSTRT_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+
+/* register PGENCTRL_H */
+# define PGENCTRL_H 33
+# define F_PTRNGENRST(x) (((x) & ((1 << 1) - 1)) << 0)
+# define F_PTRNGENRST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+# define F_PIC_SEL(x) (((x) & ((1 << 3) - 1)) << 1)
+# define F_PIC_SEL_RD(x) (((x) & (((1 << 3) - 1) << 1)) >> 1)
+# define F_PIC_YCBCR_SEL(x) (((x) & ((1 << 2) - 1)) << 4)
+# define F_PIC_YCBCR_SEL_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+
+/* register PGEN_COLOR_BAR_CTRL */
+# define PGEN_COLOR_BAR_CTRL 34
+# define F_PGEN_NUM_BAR(x) (((x) & ((1 << 3) - 1)) << 0)
+# define F_PGEN_NUM_BAR_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+/* register PGEN_COLOR_BAR_CONTROL_H */
+# define PGEN_COLOR_BAR_CONTROL_H 35
+# define F_PGEN_COLOR_UPDT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_PGEN_COLOR_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register GEN_AUDIO_CONTROL */
+# define GEN_AUDIO_CONTROL 36
+# define F_AUDIO_START(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_AUDIO_START_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+# define F_AUDIO_RESET(x) (((x) & ((1 << 1) - 1)) << 2)
+# define F_AUDIO_RESET_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+
+/* register SPDIF_CTRL_A */
+# define SPDIF_CTRL_A 37
+# define F_SPDIF_SOURCE_NUM(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_SOURCE_NUM_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_CH_NUM(x) (((x) & ((1 << 4) - 1)) << 4)
+# define F_SPDIF_CH_NUM_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+
+/* register SPDIF_CTRL_A_H */
+# define SPDIF_CTRL_A_H 38
+# define F_SPDIF_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_CLK_ACCUR(x) (((x) & ((1 << 2) - 1)) << 4)
+# define F_SPDIF_CLK_ACCUR_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+# define F_SPDIF_VALID(x) (((x) & ((1 << 1) - 1)) << 6)
+# define F_SPDIF_VALID_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+
+/* register SPDIF_CTRL_B */
+# define SPDIF_CTRL_B 39
+# define F_SPDIF_WORD_LENGTH(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_WORD_LENGTH_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_ORG_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 4)
+# define F_SPDIF_ORG_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+
+/* register SPDIF_CTRL_B_H */
+# define SPDIF_CTRL_B_H 40
+# define F_CATEGORY_MODE(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_CATEGORY_MODE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register AUDIO_DIV_EN */
+# define AUDIO_DIV_EN 45
+# define F_AGEN_60958_I2S(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_AGEN_60958_I2S_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+# define F_AGEN_PRL_SUBFRAME(x) (((x) & ((1 << 1) - 1)) << 2)
+# define F_AGEN_PRL_SUBFRAME_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+# define F_AGEN_SAMPLES_DATA(x) (((x) & ((1 << 1) - 1)) << 3)
+# define F_AGEN_SAMPLES_DATA_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+#endif /*AVGEN */
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * avgen_drv.c
+ *
+ ******************************************************************************
+ */
+
+#include "mhl_hdtx_top.h"
+#include "address.h"
+#include "avgen.h"
+#include "avgen_drv.h"
+#include "util.h"
+#include "externs.h"
+
+#define ADDR_AVGEN 0x80000
+
+CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol,
+ VIC_PXL_ENCODING_FORMAT format)
+{
+ /*CDN_API_STATUS ret; */
+ /*GENERAL_Read_Register_response resp; */
+ unsigned int pixelClockFreq = CDN_API_Get_PIXEL_FREQ_KHZ_ClosetVal
+ (vic_table[vicMode][PIXEL_FREQ_KHZ], protocol);
+ unsigned int v_h_polarity =
+ ((vic_table[vicMode][HSYNC_POL] == ACTIVE_LOW) ? 0 : 1) +
+ ((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2);
+ unsigned int front_porche_l = vic_table[vicMode][FRONT_PORCH] - 256 *
+ ((unsigned int)vic_table[vicMode][FRONT_PORCH] / 256);
+ unsigned int front_porche_h = vic_table[vicMode][FRONT_PORCH] / 256;
+ unsigned int back_porche_l = vic_table[vicMode][BACK_PORCH] - 256 *
+ ((unsigned int)vic_table[vicMode][BACK_PORCH] / 256);
+ unsigned int back_porche_h = vic_table[vicMode][BACK_PORCH] / 256;
+ unsigned int active_slot_l = vic_table[vicMode][H_BLANK] - 256 *
+ ((unsigned int)vic_table[vicMode][H_BLANK] / 256);
+ unsigned int active_slot_h = vic_table[vicMode][H_BLANK] / 256;
+ unsigned int frame_lines_l = vic_table[vicMode][V_TOTAL] - 256 *
+ ((unsigned int)vic_table[vicMode][V_TOTAL] / 256);
+ unsigned int frame_lines_h = vic_table[vicMode][V_TOTAL] / 256;
+ unsigned int line_width_l = vic_table[vicMode][H_TOTAL] - 256 *
+ ((unsigned int)vic_table[vicMode][H_TOTAL] / 256);
+ unsigned int line_width_h = vic_table[vicMode][H_TOTAL] / 256;
+ unsigned int vsync_lines = vic_table[vicMode][VSYNC];
+ unsigned int eof_lines = vic_table[vicMode][TYPE_EOF];
+ unsigned int sof_lines = vic_table[vicMode][SOF];
+ unsigned int interlace_progressive =
+ (vic_table[vicMode][I_P] == INTERLACED) ? 2 : 0;
+ unsigned int set_vif_clock = 0;
+
+ /*needed for HDMI /////////////////////////////// */
+ /*unsigned int hblank = vic_table[vicMode][H_BLANK]; */
+ /*unsigned int hactive = vic_table[vicMode][H_TOTAL]-hblank; */
+ /*unsigned int vblank = vsync_lines+eof_lines+sof_lines; */
+ /*unsigned int vactive = vic_table[vicMode][V_TOTAL]-vblank; */
+ /*unsigned int hfront = vic_table[vicMode][FRONT_PORCH]; */
+ /*unsigned int hback = vic_table[vicMode][BACK_PORCH]; */
+ /*unsigned int vfront = eof_lines; */
+ /*unsigned int hsync = hblank-hfront-hback; */
+ /*unsigned int vsync = vsync_lines; */
+ /*unsigned int vback = sof_lines; */
+ unsigned int set_CLK_SEL = 0;
+ unsigned int set_REF_CLK_SEL = 0;
+ unsigned int set_pll_CLK_IN = 0;
+ unsigned int set_pll_clkfbout_l = 0;
+ unsigned int set_pll_clkfbout_h = 0;
+ unsigned int set_pll_CLKOUT5_L = 0;
+ unsigned int set_pll_CLKOUT5_H = 0;
+ unsigned int set_pll2_CLKIN = 0;
+ unsigned int set_pll2_CLKFBOUT_L = 0;
+ unsigned int set_pll2_CLKFBOUT_H = 0;
+ unsigned int set_pll2_CLKOUT5_L = 0;
+ unsigned int set_pll2_CLKOUT5_H = 0;
+ /*///////////////////////////////////////////////// */
+
+ cdn_apb_write(0x1c00C6 << 2,
+ (int)(vic_table[vicMode][PIXEL_FREQ_KHZ] * 1000));
+ cdn_apb_write(0x1c00C6 << 2, (int)(pixelClockFreq));
+
+ if ((int)(pixelClockFreq) == 25) {
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ set_CLK_SEL = 4;
+ set_REF_CLK_SEL = 0;
+ set_pll_CLK_IN = 65;
+ set_pll_clkfbout_l = 4292;
+ set_pll_clkfbout_h = 128;
+ set_pll_CLKOUT5_L = 4422;
+ set_pll_CLKOUT5_H = 128;
+ set_pll2_CLKIN = 12289;
+ set_pll2_CLKFBOUT_L = 4356;
+ set_pll2_CLKFBOUT_H = 0;
+ set_pll2_CLKOUT5_L = 4552;
+ set_pll2_CLKOUT5_H = 128;
+ } else {
+ set_vif_clock = 0x300;
+ }
+ } else if ((int)pixelClockFreq == 27000) {
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ set_CLK_SEL = 5;
+ set_REF_CLK_SEL = 0;
+ set_pll_CLK_IN = 49217;
+ set_pll_clkfbout_l = 4226;
+ set_pll_clkfbout_h = 0;
+ set_pll_CLKOUT5_L = 4422;
+ set_pll_CLKOUT5_H = 128;
+ } else {
+ set_vif_clock = 0x301;
+ }
+ } else if ((int)pixelClockFreq == 54000) {
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ set_CLK_SEL = 5;
+ set_REF_CLK_SEL = 0;
+ set_pll_CLK_IN = 4096;
+ set_pll_clkfbout_l = 4226;
+ set_pll_clkfbout_h = 0;
+ set_pll_CLKOUT5_L = 4422;
+ set_pll_CLKOUT5_H = 128;
+ } else {
+ set_vif_clock = 0x302;
+ }
+ } else if (pixelClockFreq == 74250) {
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ set_CLK_SEL = 1;
+ set_pll_CLK_IN = 74;
+ } else {
+ set_vif_clock = 0x303;
+ }
+ } else if (pixelClockFreq == 148500) {
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ set_CLK_SEL = 0;
+ set_pll_CLK_IN = 148;
+ } else {
+ set_vif_clock = 0x304;
+ }
+ } else if ((int)pixelClockFreq == 108000) {
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ set_CLK_SEL = 5;
+ set_REF_CLK_SEL = 2;
+ set_pll_CLK_IN = 8258;
+ set_pll_clkfbout_l = 4616;
+ set_pll_clkfbout_h = 0;
+ set_pll_CLKOUT5_L = 4422;
+ set_pll_CLKOUT5_H = 128;
+ } else {
+ set_vif_clock = 0x305;
+ }
+ } else {
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ set_CLK_SEL = 1;
+ set_pll_CLK_IN = pixelClockFreq;
+ } else {
+ set_vif_clock = 0;
+ }
+ }
+ unsigned int start_pgen = 128;
+ /*unsigned int temp; */
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ if (cdn_apb_write(0x0c0001 << 2,
+ ((0) + (2 * set_CLK_SEL) + (16 * 0) +
+ (32 * 0) + (64 * 3) + (65536 * 3) +
+ (1048576 * set_REF_CLK_SEL))))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c00C6 << 2, set_pll_CLK_IN))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c00CC << 2, set_pll_clkfbout_l))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c00CD << 2, set_pll_clkfbout_h))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c00CE << 2, set_pll_CLKOUT5_L))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c00CF << 2, set_pll_CLKOUT5_H))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c0086 << 2, set_pll2_CLKIN))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c008C << 2, set_pll2_CLKFBOUT_L))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c008D << 2, set_pll2_CLKFBOUT_H))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c008E << 2, set_pll2_CLKOUT5_L))
+ return CDN_ERR;
+ if (cdn_apb_write(0x1c008F << 2, set_pll2_CLKOUT5_H))
+ return CDN_ERR;
+ if (cdn_apb_write(0x0c0001 << 2,
+ ((1) + (2 * set_CLK_SEL) + (16 * 0) +
+ (32 * 0) + (64 * 3) + (65536 * 3) +
+ (1048576 * set_REF_CLK_SEL))))
+ return CDN_ERR;
+ }
+
+ if (cdn_apb_write((ADDR_AVGEN + HDMIPOL) << 2, v_h_polarity))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDMI_FRONT_PORCHE_L) << 2,
+ front_porche_l))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDFP) << 2, front_porche_h))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDBP) << 2, back_porche_l))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDMI_BACK_PORCHE_H) << 2,
+ back_porche_h))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDAS) << 2, active_slot_l))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDMI_ACTIVE_SLOT_H) << 2,
+ active_slot_h))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDFL) << 2, frame_lines_l))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDMI_FRAME_LINES_H) << 2,
+ frame_lines_h))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDLW) << 2, line_width_l))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDMI_LINE_WIDTH_H) << 2, line_width_h))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDVL) << 2, vsync_lines))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDEL) << 2, eof_lines))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + HDSL) << 2, sof_lines))
+ return CDN_ERR;
+ if (cdn_apb_write((ADDR_AVGEN + PTRNGENFF) << 2, interlace_progressive))
+ return CDN_ERR;
+
+ if (protocol == CDN_HDMITX_TYPHOON) {
+ switch (format) {
+ case PXL_RGB:
+
+ if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+ F_PIC_SEL(1) | F_PIC_YCBCR_SEL(0)))
+ return CDN_ERR;
+ break;
+
+ case YCBCR_4_4_4:
+ if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+ F_PIC_SEL(2) | F_PIC_YCBCR_SEL(0)))
+ return CDN_ERR;
+
+ break;
+
+ case YCBCR_4_2_2:
+ if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+ F_PIC_SEL(2) | F_PIC_YCBCR_SEL(1)))
+ return CDN_ERR;
+
+ break;
+
+ case YCBCR_4_2_0:
+ if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+ F_PIC_SEL(2) | F_PIC_YCBCR_SEL(2)))
+ return CDN_ERR;
+
+ break;
+ case Y_ONLY:
+ /*not exist in hdmi */
+ break;
+ }
+ } else {
+ if (set_vif_clock != 0)
+ if (cdn_apb_write(0xC0006 << 2, set_vif_clock))
+ return CDN_ERR;
+ }
+
+ if (cdn_apb_write((ADDR_AVGEN + PGENCTRL) << 2, start_pgen))
+ return CDN_ERR;
+
+ return CDN_OK;
+}
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * avgen_drv.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef AVGEN_DRV_H_
+# define AVGEN_DRV_H_
+
+#ifndef __UBOOT__
+# include <stdint.h>
+#else
+#include <common.h>
+#endif
+
+# include "vic_table.h"
+# include "API_General.h"
+# include "defs.h"
+
+/**
+ * \brief set avgen according to mode and vic table, user that doesnt have
+ * cadence AVGEN, need to implement this function on user
+ * platform
+ */
+CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol,
+ VIC_PXL_ENCODING_FORMAT format);
+
+#endif
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * defs.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _DEFS_H_
+#define _DEFS_H_
+
+typedef enum {
+ CDN_DPTX ,
+ CDN_HDMITX_TYPHOON,
+ CDN_HDMITX_KIRAN,
+} CDN_PROTOCOL_TYPE;
+
+#endif /*_DEFS_H_ */
+
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * edid_parser.c
+ *
+ ******************************************************************************
+ */
+
+#include "edid_parser.h"
+
+static EDID_PARSER_RESULT edid_parse_dtd(S_DTD_DATA *descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_DTD;
+ descriptor->header.tag = 0;
+
+ descriptor->pixel_clock = raw_data[raw_data_index];
+ descriptor->pixel_clock +=
+ (unsigned short)raw_data[raw_data_index + 1] << 8;
+
+ descriptor->horizontal_addressable_video = raw_data[raw_data_index + 2];
+ descriptor->horizontal_addressable_video +=
+ ((unsigned short)raw_data[raw_data_index + 4] & 0xF0) << 4;
+ descriptor->horizontal_blanking = raw_data[raw_data_index + 3];
+ descriptor->horizontal_blanking +=
+ ((unsigned short)raw_data[raw_data_index + 4] & 0x0F) << 8;
+
+ descriptor->vertical_addressable_video = raw_data[raw_data_index + 5];
+ descriptor->vertical_addressable_video +=
+ ((unsigned short)raw_data[raw_data_index + 7] & 0xF0) << 4;
+ descriptor->vertical_blanking = raw_data[raw_data_index + 6];
+ descriptor->vertical_blanking +=
+ ((unsigned short)raw_data[raw_data_index + 7] & 0x0F) << 8;
+
+ descriptor->horizontal_front_porch = raw_data[raw_data_index + 8];
+ descriptor->horizontal_front_porch +=
+ ((unsigned short)raw_data[raw_data_index + 11] & 0xC0) << 2;
+ descriptor->horizontal_sync_pulse_width = raw_data[raw_data_index + 9];
+ descriptor->horizontal_sync_pulse_width +=
+ ((unsigned short)raw_data[raw_data_index + 11] & 0x30) << 4;
+
+ descriptor->vertical_front_porch =
+ (raw_data[raw_data_index + 10] & 0xF0) >> 4;
+ descriptor->vertical_front_porch +=
+ (raw_data[raw_data_index + 11] & 0x0C) << 2;
+ descriptor->vertical_sync_pulse_width =
+ raw_data[raw_data_index + 10] & 0x0F;
+ descriptor->vertical_sync_pulse_width +=
+ (raw_data[raw_data_index + 11] & 0x03) << 4;
+
+ descriptor->horizontal_addressable_video_image_size =
+ raw_data[raw_data_index + 12];
+ descriptor->horizontal_addressable_video_image_size +=
+ ((unsigned short)raw_data[raw_data_index + 14] & 0xF0) << 4;
+ descriptor->vertical_addressable_video_image_size =
+ raw_data[raw_data_index + 13];
+ descriptor->vertical_addressable_video_image_size +=
+ ((unsigned short)raw_data[raw_data_index + 14] & 0x0F) << 8;
+
+ descriptor->horizontal_border = raw_data[raw_data_index + 15];
+ descriptor->vertical_border = raw_data[raw_data_index + 16];
+
+ descriptor->signal_features = raw_data[raw_data_index + 17];
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_serial_number(S_SERIAL_NUMBER_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+ descriptor->header.type = DESCRIPTOR_TYPE_SERIAL_NUMBER;
+ descriptor->header.tag = 0xFF;
+
+ int idx;
+ for (idx = 0; idx < 13; idx++)
+ descriptor->serial_number[idx] =
+ raw_data[raw_data_index + 5 + idx];
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_data_string(S_DATA_STRING_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+ descriptor->header.type = DESCRIPTOR_TYPE_DATA_STRING;
+ descriptor->header.tag = 0xFE;
+ int idx;
+ for (idx = 0; idx < 13; idx++)
+ descriptor->data_string[idx] =
+ raw_data[raw_data_index + 5 + idx];
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_range_limits(S_RANGE_LIMITS_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_RANGE_LIMITS;
+ descriptor->header.tag = 0xFD;
+
+ descriptor->offset_flags = raw_data[raw_data_index + 4];
+ descriptor->min_vertical_rate = raw_data[raw_data_index + 5];
+ descriptor->max_vertical_rate = raw_data[raw_data_index + 6];
+ descriptor->min_horizontal_rate = raw_data[raw_data_index + 7];
+ descriptor->max_horizontal_rate = raw_data[raw_data_index + 8];
+ descriptor->max_pixel_clock = raw_data[raw_data_index + 9];
+
+ switch (raw_data[raw_data_index + 10]) {
+ case 0x00:
+ descriptor->type = VIDEO_TIMING_DEFAULT_GTF;
+ break;
+ case 0x01:
+ descriptor->type = VIDEO_TIMING_RANGE_LIMITS_ONLY;
+ break;
+ case 0x02:
+ descriptor->type = VIDEO_TIMING_SECONDARY_GTF;
+ S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *timing_type_gtf =
+ (S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *)
+ descriptor->suport_flags;
+ timing_type_gtf->start_break_frequency =
+ raw_data[raw_data_index + 12];
+ timing_type_gtf->c = raw_data[raw_data_index + 13];
+ timing_type_gtf->m = raw_data[raw_data_index + 14];
+ timing_type_gtf->m +=
+ (unsigned short)raw_data[raw_data_index + 15] << 8;
+ timing_type_gtf->k = raw_data[raw_data_index + 16];
+ timing_type_gtf->j = raw_data[raw_data_index + 17];
+ break;
+ case 0x04:
+ descriptor->type = VIDEO_TIMING_CVT;
+ S_RANGE_LIMITS_VIDEO_TIMING_CVT *timing_type_cvt =
+ (S_RANGE_LIMITS_VIDEO_TIMING_CVT *)descriptor->
+ suport_flags;
+ timing_type_cvt->cvt_version = raw_data[raw_data_index + 11];
+ timing_type_cvt->additional_pixel_clock_precision =
+ raw_data[raw_data_index + 12] >> 2;
+ timing_type_cvt->max_active_pixels =
+ raw_data[raw_data_index + 13];
+ timing_type_cvt->max_active_pixels +=
+ (unsigned short)(raw_data[raw_data_index + 12] & 0x03)
+ << 8;
+ timing_type_cvt->supported_ar =
+ raw_data[raw_data_index + 14] >> 3;
+ timing_type_cvt->preferred_ar =
+ raw_data[raw_data_index + 15] >> 5;
+ timing_type_cvt->blanking_support =
+ (raw_data[raw_data_index + 15] & 0x18) >> 3;
+ timing_type_cvt->supported_scalling =
+ raw_data[raw_data_index + 16] >> 4;
+ timing_type_cvt->preferred_vertical_refresh_rate =
+ raw_data[raw_data_index + 17];
+ break;
+ }
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_product_name(S_PRODUCT_NAME_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_PRODUCT_NAME;
+ descriptor->header.tag = 0xFC;
+ int idx;
+ for (idx = 0; idx < 13; idx++)
+ descriptor->product_name[idx] =
+ raw_data[raw_data_index + 5 + idx];
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_color_point(S_COLOR_POINT_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_COLOR_POINT;
+ descriptor->header.tag = 0xFB;
+ descriptor->white_point_index_1 = raw_data[raw_data_index + 5];
+ descriptor->white_x_1 = (raw_data[raw_data_index + 6] & 0x0C) >> 2;
+ descriptor->white_x_1 +=
+ (unsigned short)raw_data[raw_data_index + 7] << 2;
+ descriptor->white_y_1 = raw_data[raw_data_index + 6] & 0x03;
+ descriptor->white_y_1 +=
+ (unsigned short)raw_data[raw_data_index + 8] << 2;
+ descriptor->gamma_1 = raw_data[raw_data_index + 9];
+
+ descriptor->white_point_index_2 = raw_data[raw_data_index + 10];
+ descriptor->white_x_2 = (raw_data[raw_data_index + 11] & 0x0C) >> 2;
+ descriptor->white_x_2 +=
+ (unsigned short)raw_data[raw_data_index + 12] << 2;
+ descriptor->white_y_2 = raw_data[raw_data_index + 11] & 0x03;
+ descriptor->white_y_2 +=
+ (unsigned short)raw_data[raw_data_index + 13] << 2;
+ descriptor->gamma_2 = raw_data[raw_data_index + 14];
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_standard_timing(S_STANDARD_TIMING_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_STANDARD_TIMING;
+ descriptor->header.tag = 0xFA;
+ int idx;
+ for (idx = 0; idx < 6; idx++) {
+ descriptor->standard_timings[idx] =
+ raw_data[raw_data_index + 5 + 2 * idx];
+ descriptor->standard_timings[idx] +=
+ (unsigned short)raw_data[raw_data_index + 5 + 2 * idx +
+ 1];
+ }
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_color_management(S_COLOR_MANAGEMENT_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_COLOR_MANAGEMENT;
+ descriptor->header.tag = 0xF9;
+
+ descriptor->version = raw_data[raw_data_index + 5];
+
+ descriptor->red_a3 = raw_data[raw_data_index + 6];
+ descriptor->red_a3 += (unsigned short)raw_data[raw_data_index + 7] << 8;
+ descriptor->red_a2 = raw_data[raw_data_index + 8];
+ descriptor->red_a2 += (unsigned short)raw_data[raw_data_index + 9] << 8;
+
+ descriptor->green_a3 = raw_data[raw_data_index + 10];
+ descriptor->green_a3 +=
+ (unsigned short)raw_data[raw_data_index + 11] << 8;
+ descriptor->green_a2 = raw_data[raw_data_index + 12];
+ descriptor->green_a2 +=
+ (unsigned short)raw_data[raw_data_index + 13] << 8;
+
+ descriptor->blue_a3 = raw_data[raw_data_index + 14];
+ descriptor->blue_a3 +=
+ (unsigned short)raw_data[raw_data_index + 15] << 8;
+ descriptor->blue_a2 = raw_data[raw_data_index + 16];
+ descriptor->blue_a2 +=
+ (unsigned short)raw_data[raw_data_index + 17] << 8;
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_cvt_timing_codes(S_CVT_TIMING_CODES_DATA *
+ descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_CVT_TIMING_CODES;
+ descriptor->header.tag = 0xF8;
+ descriptor->version = raw_data[raw_data_index + 5];
+
+ int idx;
+ for (idx = 0; idx < 4; idx++) {
+ descriptor->addressable_lines[idx] =
+ raw_data[raw_data_index + 6 + idx * 3];
+ descriptor->addressable_lines[idx] +=
+ (unsigned short)(raw_data[raw_data_index + 7 + idx * 3]
+ & 0xF0) << 4;
+ descriptor->aspect_ratio[idx] =
+ (raw_data[raw_data_index + 7 + idx * 3] & 0x0C) >> 2;
+ descriptor->preferred_vertical_rate[idx] =
+ (raw_data[raw_data_index + 8 + idx * 3] & 0x60) >> 5;
+ descriptor->supported_vertical_rate_and_blanking[idx] =
+ raw_data[raw_data_index + 8 + idx * 3] & 0x1F;
+ }
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT
+edid_parse_established_timings_3(S_ESTABLISHED_TIMINGS_3_DATA *descriptor,
+ unsigned char *raw_data)
+{
+ unsigned int raw_data_index = 0;
+
+ descriptor->header.type = DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3;
+ descriptor->header.tag = 0xF7;
+ descriptor->version = raw_data[raw_data_index + 5];
+ int idx;
+ for (idx = 0; idx < 6; idx++) {
+ descriptor->established_timings[idx] =
+ raw_data[raw_data_index + 6 + idx];
+ }
+
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_dummy(S_DUMMY_DATA *descriptor,
+ unsigned char *raw_data)
+{
+ descriptor->header.type = DESCRIPTOR_TYPE_DUMMY;
+ descriptor->header.tag = 0x10;
+ return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT
+edid_parse_manufacturer_specific(S_MANUFACTURER_SPECIFIC_DATA *descriptor,
+ unsigned char *raw_data, unsigned char tag)
+{
+ descriptor->header.type = DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC;
+ descriptor->header.tag = tag;
+
+ return EDID_PARSER_SUCCESS;
+}
+
+EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data,
+ unsigned int len)
+{
+ unsigned int raw_data_index = 0;
+ unsigned char sum = 0;
+ /*CHECK SUM OF BYTES IN BLOCK0 */
+ for (raw_data_index = 0; raw_data_index < EDID_LENGTH; raw_data_index++)
+ sum += raw_data[raw_data_index];
+
+ if (sum != 0)
+ return EDID_PARSER_ERROR;
+
+ /*READ HEADER */
+ for (raw_data_index = 0; raw_data_index < EDID_HEADER_LENGTH;
+ raw_data_index++)
+ edid->header[raw_data_index] = raw_data[raw_data_index];
+
+ /*READ VENDOR & PRODUCT IDENTIFICATION */
+ /*manufacturer name */
+ edid->manufacturer_name[0] = ((raw_data[8] & 0x7C) >> 2) + 0x40;
+ edid->manufacturer_name[1] =
+ ((raw_data[8] & 0x03) << 3) + ((raw_data[9] & 0xE0) >> 5) +
+ 0x40;
+ edid->manufacturer_name[2] = ((raw_data[9] & 0x1F)) + 0x40;
+ edid->manufacturer_name[3] = 0;
+
+ /*product code */
+ edid->product_code = (raw_data[10]);
+ edid->product_code += ((unsigned short)raw_data[11]) << 8;
+
+ /*serial number */
+ edid->serial_number = raw_data[12];
+ edid->serial_number += (unsigned int)raw_data[13] << 8;
+ edid->serial_number += (unsigned int)raw_data[14] << 16;
+ edid->serial_number += (unsigned int)raw_data[15] << 24;
+
+ /*week of manufacture */
+ edid->week = raw_data[16];
+
+ /*year of manufacture */
+ edid->year = raw_data[17];
+
+ /*EDID STRUCTURE VERSION & REVISION */
+ edid->edid_version = ((unsigned short)raw_data[18] << 8) + raw_data[19];
+
+ /*BASIC DISPLAY PARAMETERS AND FEATURES */
+ /*video input definition */
+ edid->video_input_definition = raw_data[20];
+
+ /*horizontal screen size */
+ edid->horizontal_size = raw_data[21];
+
+ /*vertical screen size */
+ edid->vertical_size = raw_data[22];
+
+ /*display transfer characteristic */
+ edid->gamma = raw_data[23];
+
+ /*feature support */
+ edid->feature_support = raw_data[24];
+
+ /*COLOR CHARACTERISTIC */
+ /*red */
+ edid->chromacity_coorditates_red_x = (raw_data[25] & 0xC0) >> 6;
+ edid->chromacity_coorditates_red_x += (unsigned short)raw_data[27] << 2;
+ edid->chromacity_coorditates_red_y = (raw_data[25] & 0x30) >> 4;
+ edid->chromacity_coorditates_red_y += (unsigned short)raw_data[28] << 2;
+
+ /*green */
+ edid->chromacity_coorditates_green_x = (raw_data[25] & 0x0C) >> 2;
+ edid->chromacity_coorditates_green_x +=
+ (unsigned short)raw_data[29] << 2;
+ edid->chromacity_coorditates_green_y = (raw_data[25] & 0x03);
+ edid->chromacity_coorditates_green_y +=
+ (unsigned short)raw_data[30] << 2;
+
+ /*blue */
+ edid->chromacity_coorditates_blue_x = (raw_data[26] & 0xC0) >> 6;
+ edid->chromacity_coorditates_blue_x +=
+ (unsigned short)raw_data[31] << 2;
+ edid->chromacity_coorditates_blue_y = (raw_data[26] & 0x30) >> 4;
+ edid->chromacity_coorditates_blue_y +=
+ (unsigned short)raw_data[32] << 2;
+
+ /*blue */
+ edid->chromacity_coorditates_white_x = (raw_data[26] & 0x0C) >> 2;
+ edid->chromacity_coorditates_white_x +=
+ (unsigned short)raw_data[33] << 2;
+ edid->chromacity_coorditates_white_y = (raw_data[26] & 0x03);
+ edid->chromacity_coorditates_white_y +=
+ (unsigned short)raw_data[34] << 2;
+
+ /*ESTABLISHED TIMINGS */
+ edid->established_timing_1 = raw_data[35];
+ edid->established_timing_2 = raw_data[36];
+ edid->manufacturer_timing = raw_data[37];
+
+ /*STANDARD TIMINGS */
+ for (raw_data_index = 0; raw_data_index < 8; raw_data_index++) {
+ edid->standard_timings[raw_data_index] =
+ raw_data[38 + (2 * raw_data_index)];
+ edid->standard_timings[raw_data_index] +=
+ (unsigned short)raw_data[38 + (2 * raw_data_index + 1)];
+ }
+ /*extensions */
+ edid->extensions = raw_data[126];
+
+ /*DESCRIPTORS */
+ unsigned int descriptor_index;
+ raw_data_index = 54;
+ for (descriptor_index = 0; descriptor_index < 4; descriptor_index++) {
+ if (raw_data[raw_data_index] == 0 &&
+ raw_data[raw_data_index] == 0) {
+ /*display descriptor found */
+ unsigned char tag = raw_data[raw_data_index + 3];
+ if (tag == 0xFF) {
+ /*display product serial number */
+ S_SERIAL_NUMBER_DATA *descriptor =
+ (S_SERIAL_NUMBER_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_serial_number
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xFE) {
+ /*alphanumeric data string */
+ S_DATA_STRING_DATA *descriptor =
+ (S_DATA_STRING_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_data_string
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xFD) {
+ /*display range limits */
+ S_RANGE_LIMITS_DATA *descriptor =
+ (S_RANGE_LIMITS_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_range_limits
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xFC) {
+ /*display product name */
+ S_PRODUCT_NAME_DATA *descriptor =
+ (S_PRODUCT_NAME_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_product_name
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xFB) {
+ /*color point data */
+ S_COLOR_POINT_DATA *descriptor =
+ (S_COLOR_POINT_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_color_point
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xFA) {
+ /*standard timing identifications */
+ S_STANDARD_TIMING_DATA *descriptor =
+ (S_STANDARD_TIMING_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_standard_timing
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xF9) {
+ /*display color management (DCM) */
+ S_COLOR_MANAGEMENT_DATA *descriptor =
+ (S_COLOR_MANAGEMENT_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_color_management
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xF8) {
+ /*CVT 3 byte timing codes */
+ S_CVT_TIMING_CODES_DATA *descriptor =
+ (S_CVT_TIMING_CODES_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_cvt_timing_codes
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0xF7) {
+ /*established timings III */
+ S_ESTABLISHED_TIMINGS_3_DATA *descriptor =
+ (S_ESTABLISHED_TIMINGS_3_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_established_timings_3
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag == 0x10) {
+ /*dummy */
+ S_DUMMY_DATA *descriptor =
+ (S_DUMMY_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_dummy
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+
+ } else if (tag <= 0x0F) {
+ /*manufacturer specific data */
+ S_MANUFACTURER_SPECIFIC_DATA *descriptor =
+ (S_MANUFACTURER_SPECIFIC_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_manufacturer_specific
+ (descriptor, raw_data + raw_data_index,
+ tag) != EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+ }
+ } else {
+ /*detailed timing definition */
+ S_DTD_DATA *descriptor =
+ (S_DTD_DATA *)edid->
+ descriptors[descriptor_index];
+ if (edid_parse_dtd
+ (descriptor,
+ raw_data + raw_data_index) !=
+ EDID_PARSER_SUCCESS)
+ return EDID_PARSER_ERROR;
+ }
+ raw_data_index += 18;
+ }
+
+ return EDID_PARSER_SUCCESS;
+}
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * edid_parser.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef EDID_PARSER_H
+#define EDID_PARSER_H
+
+#define MAX_DESCRIPTOR_LENGTH 36
+#define MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH 12
+#define EDID_HEADER_LENGTH 8
+#define EDID_LENGTH 128
+
+typedef enum {
+ EDID_PARSER_SUCCESS,
+ EDID_PARSER_ERROR,
+} EDID_PARSER_RESULT;
+
+typedef enum {
+ DESCRIPTOR_TYPE_DTD,
+ DESCRIPTOR_TYPE_SERIAL_NUMBER,
+ DESCRIPTOR_TYPE_DATA_STRING,
+ DESCRIPTOR_TYPE_RANGE_LIMITS,
+ DESCRIPTOR_TYPE_PRODUCT_NAME,
+ DESCRIPTOR_TYPE_COLOR_POINT,
+ DESCRIPTOR_TYPE_STANDARD_TIMING,
+ DESCRIPTOR_TYPE_COLOR_MANAGEMENT,
+ DESCRIPTOR_TYPE_CVT_TIMING_CODES,
+ DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3,
+ DESCRIPTOR_TYPE_DUMMY,
+ DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC
+} EDID_DESCRIPTOR_TYPE;
+
+typedef enum {
+ VIDEO_TIMING_DEFAULT_GTF,
+ VIDEO_TIMING_RANGE_LIMITS_ONLY,
+ VIDEO_TIMING_SECONDARY_GTF,
+ VIDEO_TIMING_CVT,
+} RANGE_LIMITS_VIDEO_TIMING_TYPE;
+
+/**
+ * \brief Common descriptor header structure
+ */
+typedef struct {
+ EDID_DESCRIPTOR_TYPE type;
+ unsigned char tag;
+
+} S_DESCRIPTOR_HEADER_DATA;
+/**
+ * \brief Detailed Timing Descriptor (DTD) structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned short pixel_clock;
+ unsigned short horizontal_addressable_video;
+ unsigned short horizontal_blanking;
+ unsigned short vertical_addressable_video;
+ unsigned short vertical_blanking;
+ unsigned short horizontal_front_porch;
+ unsigned short horizontal_sync_pulse_width;
+ unsigned short vertical_front_porch;
+ unsigned short vertical_sync_pulse_width;
+ unsigned short horizontal_addressable_video_image_size;
+ unsigned short vertical_addressable_video_image_size;
+ unsigned char horizontal_border;
+ unsigned char vertical_border;
+ unsigned char signal_features;
+} S_DTD_DATA;
+
+/**
+ * \brief Serial Number Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned char serial_number[13];
+
+} S_SERIAL_NUMBER_DATA;
+
+/**
+ * \brief Data String Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ char data_string[13];
+
+} S_DATA_STRING_DATA;
+
+/**
+ * \brief Range Limits Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned char offset_flags;
+ unsigned char min_vertical_rate;
+ unsigned char max_vertical_rate;
+ unsigned char min_horizontal_rate;
+ unsigned char max_horizontal_rate;
+ unsigned char max_pixel_clock;
+ RANGE_LIMITS_VIDEO_TIMING_TYPE type;
+ unsigned char suport_flags[MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH];
+} S_RANGE_LIMITS_DATA;
+
+/**
+ * \brief Range Limits Secondary GTF Flags structure
+ */
+typedef struct {
+ unsigned char start_break_frequency;
+ unsigned char c;
+ unsigned short m;
+ unsigned char k;
+ unsigned char j;
+
+} S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF;
+
+/**
+ * \brief Range Limits CVT Flags structure
+ */
+typedef struct {
+ unsigned char cvt_version;
+ unsigned char additional_pixel_clock_precision;
+ unsigned short max_active_pixels;
+ unsigned char supported_ar;
+ unsigned char preferred_ar;
+ unsigned char blanking_support;
+ unsigned char supported_scalling;
+ unsigned char preferred_vertical_refresh_rate;
+} S_RANGE_LIMITS_VIDEO_TIMING_CVT;
+
+/**
+ * \brief Product Name Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ char product_name[13];
+
+} S_PRODUCT_NAME_DATA;
+
+/**
+ * \brief Color point Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned char white_point_index_1;
+ unsigned short white_x_1;
+ unsigned short white_y_1;
+ unsigned char gamma_1;
+ unsigned char white_point_index_2;
+ unsigned short white_x_2;
+ unsigned short white_y_2;
+ unsigned char gamma_2;
+} S_COLOR_POINT_DATA;
+
+/**
+ * \brief Standard Timing Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned short standard_timings[6];
+} S_STANDARD_TIMING_DATA;
+
+/**
+ * \brief Color Management Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned char version;
+ unsigned short red_a3;
+ unsigned short red_a2;
+ unsigned short green_a3;
+ unsigned short green_a2;
+ unsigned short blue_a3;
+ unsigned short blue_a2;
+} S_COLOR_MANAGEMENT_DATA;
+
+/**
+ * \brief CVT 3 Byte Code Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned char version;
+ unsigned short addressable_lines[4];
+ unsigned char aspect_ratio[4];
+ unsigned char preferred_vertical_rate[4];
+ unsigned char supported_vertical_rate_and_blanking[4];
+
+} S_CVT_TIMING_CODES_DATA;
+
+/**
+ * \brief Established Timings 3 Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned char version;
+ unsigned char established_timings[6];
+} S_ESTABLISHED_TIMINGS_3_DATA;
+
+/**
+ * \brief Dummy Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+} S_DUMMY_DATA;
+
+/**
+ * \brief Manufacturer Specific Descriptor structure
+ */
+typedef struct {
+ S_DESCRIPTOR_HEADER_DATA header;
+ unsigned char desc_data[18];
+} S_MANUFACTURER_SPECIFIC_DATA;
+
+/**
+ * \brief CEA-861 extension structure
+ */
+typedef struct {
+ unsigned char revision;
+ unsigned char underscan;
+ unsigned char audio;
+} S_CEA861_DATA;
+
+/**
+ * \brief Extended Display Identification Data (EDID) structure
+ */
+typedef struct {
+ unsigned char header[8];
+ char manufacturer_name[4];
+ unsigned short product_code;
+ unsigned int serial_number;
+ unsigned char week;
+ unsigned short year;
+ unsigned short edid_version;
+ unsigned char video_input_definition;
+ unsigned char horizontal_size;
+ unsigned char vertical_size;
+ unsigned char gamma;
+ unsigned char feature_support;
+ unsigned short chromacity_coorditates_red_x;
+ unsigned short chromacity_coorditates_red_y;
+ unsigned short chromacity_coorditates_green_x;
+ unsigned short chromacity_coorditates_green_y;
+ unsigned short chromacity_coorditates_blue_x;
+ unsigned short chromacity_coorditates_blue_y;
+ unsigned short chromacity_coorditates_white_x;
+ unsigned short chromacity_coorditates_white_y;
+ unsigned char established_timing_1;
+ unsigned char established_timing_2;
+ unsigned char manufacturer_timing;
+ unsigned short standard_timings[8];
+ unsigned char descriptors[4][MAX_DESCRIPTOR_LENGTH];
+ unsigned char extensions;
+} S_EDID_DATA;
+
+EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data,
+ unsigned int len);
+
+#endif /* EDID_PARSER_H */
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
#define GENERAL_WRITE_REGISTER 0x05
#define GENERAL_WRITE_FIELD 0x06
#define GENERAL_READ_REGISTER 0x07
+#define GENERAL_GET_HPD_STATE 0x11
#define GENERAL_TEST_TRNG_SIMPLE 0xF0
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * hdmi.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _HDMI__
+#define _HDMI__
+/* ONLY ENUMS AND #DEFINES IN THIS FILE *
+ * THIS FILE WILL BE USED IN HOST'S API */
+
+#define EDID_SLAVE_ADDRESS 0x50
+#define EDID_SEGMENT_SLAVE_ADDRESS 0x30
+#define SCDC_SLAVE_ADDRESS 0x54
+
+typedef enum {
+ HDMI_TX_READ,
+ HDMI_TX_WRITE,
+ HDMI_TX_UPDATE_READ,
+ HDMI_TX_EDID,
+ HDMI_TX_EVENTS,
+ HDMI_TX_HPD_STATUS,
+ HDMI_TX_DEBUG_ECHO = 0xAA,
+ HDMI_TX_TEST = 0xBB,
+ HDMI_TX_EDID_INTERNAL = 0xF0,
+} HDMI_TX_OPCODE;
+
+typedef enum {
+ HDMI_I2C_ACK,
+ HDMI_I2C_NACK,
+ HDMI_I2C_TO,
+ HDMI_I2C_ARB_LOST,
+ HDMI_I2C_RRTO,
+ HDMI_I2C_RRT,
+ /** when i2c hardware didn't respond after some time */
+ HDMI_I2C_HW_TO,
+ HDMI_I2C_ERR /*unspecified error */
+} HDMI_I2C_STATUS;
+
+typedef enum {
+ HDMI_RX_SET_EDID,
+ HDMI_RX_SCDC_SET,
+ HDMI_RX_SCDC_GET,
+ HDMI_RX_READ_EVENTS,
+ HDMI_RX_SET_HPD,
+
+ HDMI_RX_DEBUG_ECHO = 0xAA,
+ HDMI_RX_TEST = 0xBB,
+} HDMI_RX_OPCODE;
+
+typedef enum {
+ HDMI_SCDC_SINK_VER,
+ HDMI_SCDC_SOURCE_VER,
+} HDMI_SCDC_FIELD;
+
+/*/////////////////////////////////////// */
+/*/////////////////////////////////////// */
+typedef struct {
+ unsigned char sink_ver;
+ unsigned char manufacturer_oui_1;
+ unsigned char manufacturer_oui_2;
+ unsigned char manufacturer_oui_3;
+ unsigned char devId[8];
+ unsigned char hardware_major_rev;
+ unsigned char hardware_minor_rev;
+ unsigned char software_major_rev;
+ unsigned char software_minor_rev;
+ unsigned char manufacturerSpecific[34];
+} S_HDMI_SCDC_SET_MSG;
+
+typedef struct {
+ unsigned char source_ver;
+ unsigned char TMDS_Config;
+ unsigned char config_0;
+ unsigned char manufacturerSpecific[34];
+} S_HDMI_SCDC_GET_MSG;
+
+/*hpd events location */
+#define HDMI_RX_EVENT_5V_HIGH 0
+#define HDMI_RX_EVENT_5V_LOW 1
+#define HDMI_TX_EVENT_reserved 2
+#define HDMI_RX_EVENT_5V_VAL 3
+
+#endif /*_HDMI__ */
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * mhl_hdtx_top.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef MHL_HDTX_TOP_H_
+#define MHL_HDTX_TOP_H_
+
+/* register SCHEDULER_H_SIZE */
+#define SCHEDULER_H_SIZE 0
+#define F_H_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_H_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_H_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_H_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register SCHEDULER_V_SIZE */
+#define SCHEDULER_V_SIZE 1
+#define F_V_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_V_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_V_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_V_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register SCHEDULER_KEEP_OUT */
+#define SCHEDULER_KEEP_OUT 2
+#define F_HKEEP_OUT(x) (((x) & ((1 << 9) - 1)) << 0)
+#define F_HKEEP_OUT_RD(x) (((x) & (((1 << 9) - 1) << 0)) >> 0)
+#define F_VKEEP_OUT_START(x) (((x) & ((1 << 11) - 1)) << 9)
+#define F_VKEEP_OUT_START_RD(x) (((x) & (((1 << 11) - 1) << 9)) >> 9)
+#define F_VKEEP_OUT_ZONE(x) (((x) & ((1 << 8) - 1)) << 20)
+#define F_VKEEP_OUT_ZONE_RD(x) (((x) & (((1 << 8) - 1) << 20)) >> 20)
+
+/* register HDTX_SIGNAL_FRONT_WIDTH */
+#define HDTX_SIGNAL_FRONT_WIDTH 3
+#define F_HFRONT(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HFRONT_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VFRONT(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VFRONT_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_SIGNAL_SYNC_WIDTH */
+#define HDTX_SIGNAL_SYNC_WIDTH 4
+#define F_HSYNC(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HSYNC_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VSYNC(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VSYNC_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_SIGNAL_BACK_WIDTH */
+#define HDTX_SIGNAL_BACK_WIDTH 5
+#define F_HBACK(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HBACK_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VBACK(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VBACK_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_CONTROLLER */
+#define HDTX_CONTROLLER 6
+#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_HDMI_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_VIF_DATA_WIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+#define F_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_IL_PROG(x) (((x) & ((1 << 2) - 1)) << 5)
+#define F_IL_PROG_RD(x) (((x) & (((1 << 2) - 1) << 5)) >> 5)
+#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7)
+#define F_PIC_3D_RD(x) (((x) & (((1 << 4) - 1) << 7)) >> 7)
+#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_BCH_EN_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11)
+#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_GCP_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_SET_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_SET_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13)
+#define F_CLEAR_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 14)
+#define F_CLEAR_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 14)) >> 14)
+#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15)
+#define F_DATA_EN_RD(x) (((x) & (((1 << 1) - 1) << 15)) >> 15)
+#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16)
+#define F_HDMI_ENCODING_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16)
+#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_HDMI2_PREAMBLE_EN_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18)
+#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19)
+#define F_HDMI2_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19)
+
+/* register HDTX_HDCP */
+#define HDTX_HDCP 7
+#define F_HDTX_HDCP_SELECT(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_HDTX_HDCP_SELECT_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_ENC_BIT(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_ENC_BIT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_HDCP_ENABLE_1P1_FEATURES(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_HDCP_ENABLE_1P1_FEATURES_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_HDCP_DELAY_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_HDCP_DELAY_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_HDCP_DELAY_FIFO_SW_START(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_HDCP_DELAY_FIFO_SW_START_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_HDCP_DOUBLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_HDCP_DOUBLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_HDCP_SINGLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_HDCP_SINGLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_HDCP_DELAY_FIFO_AFULL_THR(x) (((x) & ((1 << 4) - 1)) << 8)
+#define F_HDCP_DELAY_FIFO_AFULL_THR_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8)
+#define F_HDCP_CTRL_SW_RST(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_HDCP_CTRL_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_HDCP_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_HDCP_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13)
+
+/* register HDTX_HPD */
+#define HDTX_HPD 8
+#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0)
+#define F_HPD_VALID_WIDTH_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0)
+#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12)
+#define F_HPD_GLITCH_WIDTH_RD(x) (((x) & (((1 << 8) - 1) << 12)) >> 12)
+
+/* register HDTX_CLOCK_REG_0 */
+#define HDTX_CLOCK_REG_0 9
+#define F_DATA_REGISTER_VAL_0(x) (((x) & ((1 << 20) - 1)) << 0)
+#define F_DATA_REGISTER_VAL_0_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0)
+
+/* register HDTX_CLOCK_REG_1 */
+#define HDTX_CLOCK_REG_1 10
+#define F_DATA_REGISTER_VAL_1(x) (((x) & ((1 << 20) - 1)) << 0)
+#define F_DATA_REGISTER_VAL_1_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0)
+
+/* register HPD_PLUG_IN */
+#define HPD_PLUG_IN 11
+#define F_FILTER_HPD(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_FILTER_HPD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register HDCP_IN */
+#define HDCP_IN 12
+#define F_HDCP_ESS_STATE(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_HDCP_ESS_STATE_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_HDCP_DOUBLE_FIFO_WFULL(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_HDCP_DOUBLE_FIFO_WFULL_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_HDCP_DOUBLE_FIFO_REMPTY(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_HDCP_DOUBLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_HDCP_DOUBLE_FIFO_OVERRUN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_HDCP_DOUBLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_HDCP_DOUBLE_FIFO_UNDERRUN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_HDCP_DOUBLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_HDCP_DELAY_FIFO_EMPTY(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_HDCP_DELAY_FIFO_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_HDCP_DELAY_FIFO_FULL(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_HDCP_DELAY_FIFO_FULL_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+#define F_HDCP_SINGLE_FIFO_WFULL(x) (((x) & ((1 << 2) - 1)) << 10)
+#define F_HDCP_SINGLE_FIFO_WFULL_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10)
+#define F_HDCP_SINGLE_FIFO_REMPTY(x) (((x) & ((1 << 2) - 1)) << 12)
+#define F_HDCP_SINGLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12)
+#define F_HDCP_SINGLE_FIFO_OVERRUN(x) (((x) & ((1 << 2) - 1)) << 14)
+#define F_HDCP_SINGLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14)
+#define F_HDCP_SINGLE_FIFO_UNDERRUN(x) (((x) & ((1 << 2) - 1)) << 16)
+#define F_HDCP_SINGLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16)
+
+/* register GCP_FORCE_COLOR_DEPTH_CODING */
+#define GCP_FORCE_COLOR_DEPTH_CODING 13
+#define F_COLOR_DEPTH_VAL(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_COLOR_DEPTH_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_COLOR_DEPTH_FORCE(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_COLOR_DEPTH_FORCE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_DEFAULT_PHASE_VAL(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_DEFAULT_PHASE_VAL_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+
+/* register SSCP_POSITIONING */
+#define SSCP_POSITIONING 14
+#define F_SSCP_ROW_VAL(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_SSCP_ROW_VAL_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_SSCP_COL_VAL(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_SSCP_COL_VAL_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDCP_WIN_OF_OPP_POSITION */
+#define HDCP_WIN_OF_OPP_POSITION 15
+#define F_HDCP_WIN_OF_OPP_START(x) (((x) & ((1 << 10) - 1)) << 0)
+#define F_HDCP_WIN_OF_OPP_START_RD(x) (((x) & (((1 << 10) - 1) << 0)) >> 0)
+#define F_HDCP_WIN_OF_OPP_SIZE(x) (((x) & ((1 << 6) - 1)) << 10)
+#define F_HDCP_WIN_OF_OPP_SIZE_RD(x) (((x) & (((1 << 6) - 1) << 10)) >> 10)
+
+#endif /*MHL_HDTX_TOP */
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_car.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_CAR_H_
+#define SOURCE_CAR_H_
+
+/* register SOURCE_HDTX_CAR */
+#define SOURCE_HDTX_CAR 0
+#define F_HDTX_PIXEL_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HDTX_PIXEL_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_HDTX_PIXEL_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HDTX_PIXEL_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_HDTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_HDTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_HDTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_HDTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_HDTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_HDTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_HDTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_HDTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_HDTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_HDTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_HDTX_PHY_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_HDTX_PHY_CHAR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+
+/* register SOURCE_DPTX_CAR */
+#define SOURCE_DPTX_CAR 1
+#define F_CFG_DPTX_VIF_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_CFG_DPTX_VIF_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_CFG_DPTX_VIF_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_CFG_DPTX_VIF_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_DPTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_DPTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_DPTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_DPTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_SOURCE_AUX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_SOURCE_AUX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_SOURCE_AUX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_SOURCE_AUX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_DPTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_DPTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_DPTX_PHY_CHAR_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_DPTX_PHY_CHAR_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_DPTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_DPTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_DPTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_DPTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+#define F_DPTX_FRMR_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 10)
+#define F_DPTX_FRMR_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10)
+#define F_DPTX_FRMR_DATA_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_DPTX_FRMR_DATA_CLK_RSTN_EN_RD(x) \
+ (((x) & (((1 << 1) - 1) << 11)) >> 11)
+
+/* register SOURCE_PHY_CAR */
+#define SOURCE_PHY_CAR 2
+#define F_SOURCE_PHY_DATA_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_PHY_DATA_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_RD(x) \
+ (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_RD(x) \
+ (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_CEC_CAR */
+#define SOURCE_CEC_CAR 3
+#define F_SOURCE_CEC_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CEC_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CEC_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CEC_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register SOURCE_CBUS_CAR */
+#define SOURCE_CBUS_CAR 4
+#define F_SOURCE_CBUS_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CBUS_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register SOURCE_PKT_CAR */
+#define SOURCE_PKT_CAR 6
+#define F_SOURCE_PKT_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_PKT_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_PKT_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_PKT_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_PKT_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_PKT_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_PKT_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_PKT_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_AIF_CAR */
+#define SOURCE_AIF_CAR 7
+#define F_SOURCE_AIF_PKT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_AIF_PKT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_AIF_PKT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_AIF_PKT_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_AIF_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_AIF_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_AIF_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_AIF_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_SPDIF_CDR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_SPDIF_CDR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_SPDIF_CDR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_SPDIF_CDR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_SPDIF_MCLK_EN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_SPDIF_MCLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_SPDIF_MCLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_SPDIF_MCLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+
+/* register SOURCE_CIPHER_CAR */
+#define SOURCE_CIPHER_CAR 8
+#define F_SOURCE_CIPHER_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CIPHER_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN_RD(x) \
+ (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_CIPHER_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_CIPHER_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_RD(x) \
+ (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_CRYPTO_CAR */
+#define SOURCE_CRYPTO_CAR 9
+#define F_SOURCE_CRYPTO_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CRYPTO_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN_RD(x) \
+ (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+#endif /*SOURCE_CAR */
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_phy.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_PHY_H_
+#define SOURCE_PHY_H_
+
+/* register SHIFT_PATTERN_IN_3_0 */
+#define SHIFT_PATTERN_IN_3_0 0
+#define F_SOURCE_PHY_SHIFT_PATTERN0(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN1(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN1_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN2(x) (((x) & ((1 << 8) - 1)) << 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN2_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN3(x) (((x) & ((1 << 8) - 1)) << 24)
+#define F_SOURCE_PHY_SHIFT_PATTERN3_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24)
+
+/* register SHIFT_PATTERN_IN_4_7 */
+#define SHIFT_PATTERN_IN_4_7 1
+#define F_SOURCE_PHY_SHIFT_PATTERN4(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN4_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN5(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN5_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN6(x) (((x) & ((1 << 8) - 1)) << 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN6_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN7(x) (((x) & ((1 << 8) - 1)) << 24)
+#define F_SOURCE_PHY_SHIFT_PATTERN7_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24)
+
+/* register SHIFT_PATTERN_IN9_8 */
+#define SHIFT_PATTERN_IN9_8 2
+#define F_SOURCE_PHY_SHIFT_PATTERN8(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN9(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN9_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_SHIFT_LOAD(x) (((x) & ((1 << 1) - 1)) << 16)
+#define F_SOURCE_PHY_SHIFT_LOAD_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_SHIFT_EN(x) (((x) & ((1 << 1) - 1)) << 17)
+#define F_SOURCE_PHY_SHIFT_EN_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17)
+#define F_SOURCE_PHY_SHIFT_REPETITION(x) (((x) & ((1 << 3) - 1)) << 18)
+#define F_SOURCE_PHY_SHIFT_REPETITION_RD(x) \
+ (((x) & (((1 << 3) - 1) << 18)) >> 18)
+
+/* register PRBS_CNTRL */
+#define PRBS_CNTRL 3
+#define F_SOURCE_PHY_PRBS0_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_SOURCE_PHY_PRBS0_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_PRBS0_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_SOURCE_PHY_PRBS0_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+#define F_SOURCE_PHY_PRBS1_MODE(x) (((x) & ((1 << 2) - 1)) << 4)
+#define F_SOURCE_PHY_PRBS1_MODE_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+#define F_SOURCE_PHY_PRBS1_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 6)
+#define F_SOURCE_PHY_PRBS1_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6)
+#define F_SOURCE_PHY_PRBS2_MODE(x) (((x) & ((1 << 2) - 1)) << 8)
+#define F_SOURCE_PHY_PRBS2_MODE_RD(x) (((x) & (((1 << 2) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_PRBS2_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 10)
+#define F_SOURCE_PHY_PRBS2_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10)
+#define F_SOURCE_PHY_PRBS3_MODE(x) (((x) & ((1 << 2) - 1)) << 12)
+#define F_SOURCE_PHY_PRBS3_MODE_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12)
+#define F_SOURCE_PHY_PRBS3_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 14)
+#define F_SOURCE_PHY_PRBS3_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14)
+
+/* register PRBS_ERR_INSERTION */
+#define PRBS_ERR_INSERTION 4
+#define F_ADD_ERROR0(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_ADD_ERROR0_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_NUMBER_OF_ERRORS0(x) (((x) & ((1 << 5) - 1)) << 1)
+#define F_NUMBER_OF_ERRORS0_RD(x) (((x) & (((1 << 5) - 1) << 1)) >> 1)
+#define F_ADD_ERROR1(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_ADD_ERROR1_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_NUMBER_OF_ERRORS1(x) (((x) & ((1 << 5) - 1)) << 7)
+#define F_NUMBER_OF_ERRORS1_RD(x) (((x) & (((1 << 5) - 1) << 7)) >> 7)
+#define F_ADD_ERROR2(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_ADD_ERROR2_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_NUMBER_OF_ERRORS2(x) (((x) & ((1 << 5) - 1)) << 13)
+#define F_NUMBER_OF_ERRORS2_RD(x) (((x) & (((1 << 5) - 1) << 13)) >> 13)
+#define F_ADD_ERROR3(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_ADD_ERROR3_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18)
+#define F_NUMBER_OF_ERRORS3(x) (((x) & ((1 << 5) - 1)) << 19)
+#define F_NUMBER_OF_ERRORS3_RD(x) (((x) & (((1 << 5) - 1) << 19)) >> 19)
+
+/* register LANES_CONFIG */
+#define LANES_CONFIG 5
+#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_SOURCE_PHY_LANE0_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_SOURCE_PHY_LANE1_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4)
+#define F_SOURCE_PHY_LANE2_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6)
+#define F_SOURCE_PHY_LANE3_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6)
+#define F_SOURCE_PHY_LANE0_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_SOURCE_PHY_LANE0_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_LANE1_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_SOURCE_PHY_LANE1_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+#define F_SOURCE_PHY_LANE2_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 10)
+#define F_SOURCE_PHY_LANE2_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10)
+#define F_SOURCE_PHY_LANE3_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_SOURCE_PHY_LANE3_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11)
+#define F_SOURCE_PHY_AUX_SPARE(x) (((x) & ((1 << 4) - 1)) << 12)
+#define F_SOURCE_PHY_AUX_SPARE_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12)
+#define F_SOURCE_PHY_LANE0_POLARITY(x) (((x) & ((1 << 1) - 1)) << 16)
+#define F_SOURCE_PHY_LANE0_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_LANE1_POLARITY(x) (((x) & ((1 << 1) - 1)) << 17)
+#define F_SOURCE_PHY_LANE1_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17)
+#define F_SOURCE_PHY_LANE2_POLARITY(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_SOURCE_PHY_LANE2_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18)
+#define F_SOURCE_PHY_LANE3_POLARITY(x) (((x) & ((1 << 1) - 1)) << 19)
+#define F_SOURCE_PHY_LANE3_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19)
+#define F_SOURCE_PHY_DATA_DEL_EN(x) (((x) & ((1 << 1) - 1)) << 20)
+#define F_SOURCE_PHY_DATA_DEL_EN_RD(x) (((x) & (((1 << 1) - 1) << 20)) >> 20)
+#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21)
+#define F_SOURCE_PHY_COMB_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 21)) >> 21)
+#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22)
+#define F_SOURCE_PHY_20_10_RD(x) (((x) & (((1 << 1) - 1) << 22)) >> 22)
+
+/* register PHY_DATA_SEL */
+#define PHY_DATA_SEL 6
+#define F_SOURCE_PHY_DATA_SEL(x) (((x) & ((1 << 3) - 1)) << 0)
+#define F_SOURCE_PHY_DATA_SEL_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3)
+#define F_SOURCE_PHY_MHDP_SEL_RD(x) (((x) & (((1 << 2) - 1) << 3)) >> 3)
+
+/* register LANES_DEL_VAL */
+#define LANES_DEL_VAL 7
+#define F_SOURCE_PHY_LANE0_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_SOURCE_PHY_LANE0_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_LANE1_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 4)
+#define F_SOURCE_PHY_LANE1_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+#define F_SOURCE_PHY_LANE2_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 8)
+#define F_SOURCE_PHY_LANE2_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_LANE3_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 12)
+#define F_SOURCE_PHY_LANE3_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12)
+
+#endif /*SOURCE_PHY */
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_pif.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_PIF_H_
+#define SOURCE_PIF_H_
+
+/* register SOURCE_PIF_WR_ADDR */
+#define SOURCE_PIF_WR_ADDR 0
+#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_WR_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_WR_REQ */
+#define SOURCE_PIF_WR_REQ 1
+#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_WR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_RD_ADDR */
+#define SOURCE_PIF_RD_ADDR 2
+#define F_RD_ADDR(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_RD_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_RD_REQ */
+#define SOURCE_PIF_RD_REQ 3
+#define F_HOST_RD(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_RD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_DATA_WR */
+#define SOURCE_PIF_DATA_WR 4
+/*# define F_DATA_WR(x) (((x) & ((1 << 32) - 1)) << 0) */
+/*# define F_DATA_WR_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0) */
+#define F_DATA_WR(x) (((x) & 0xffffffff) << 0)
+#define F_DATA_WR_RD(x) (((x) & 0xffffffff) >> 0)
+
+/* register SOURCE_PIF_DATA_RD */
+#define SOURCE_PIF_DATA_RD 5
+#define F_FIFO2_DATA_OUT(x) (((x) & ((1 << 32) - 1)) << 0)
+#define F_FIFO2_DATA_OUT_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_FIFO1_FLUSH */
+#define SOURCE_PIF_FIFO1_FLUSH 6
+#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_FIFO1_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_FIFO2_FLUSH */
+#define SOURCE_PIF_FIFO2_FLUSH 7
+#define F_FIFO2_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_FIFO2_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_STATUS */
+#define SOURCE_PIF_STATUS 8
+#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE_RD(x) \
+ (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_FIFO1_FULL(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_FIFO1_FULL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_FIFO2_EMPTY(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_FIFO2_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_PIF_INTERRUPT_SOURCE */
+#define SOURCE_PIF_INTERRUPT_SOURCE 9
+#define F_HOST_WR_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_WR_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_HOST_RD_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HOST_RD_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_NONVALID_TYPE_REQUESTED_INT(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_NONVALID_TYPE_REQUESTED_INT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_PSLVERR(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_PSLVERR_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_ALLOC_WR_DONE(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_ALLOC_WR_DONE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_ALLOC_WR_ERROR(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_ALLOC_WR_ERROR_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_FIFO1_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_FIFO1_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_FIFO1_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_FIFO1_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_FIFO2_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_FIFO2_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_FIFO2_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_FIFO2_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+
+/* register SOURCE_PIF_INTERRUPT_MASK */
+#define SOURCE_PIF_INTERRUPT_MASK 10
+#define F_HOST_WR_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_WR_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_HOST_RD_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HOST_RD_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_NONVALID_TYPE_REQUESTED_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_NONVALID_TYPE_REQUESTED_INT_MASK_RD(x) \
+ (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_PSLVERR_MASK(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_PSLVERR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_ALLOC_WR_DONE_MASK(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_ALLOC_WR_DONE_MASK_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_ALLOC_WR_ERROR_MASK(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_ALLOC_WR_ERROR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_FIFO1_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_FIFO1_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_FIFO1_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_FIFO1_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_FIFO2_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_FIFO2_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_FIFO2_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_FIFO2_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+
+/* register SOURCE_PIF_PKT_ALLOC_REG */
+#define SOURCE_PIF_PKT_ALLOC_REG 11
+#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_PKT_ALLOC_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_PACKET_TYPE_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16)
+#define F_TYPE_VALID_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16)
+#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17)
+#define F_ACTIVE_IDLE_TYPE_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17)
+
+/* register SOURCE_PIF_PKT_ALLOC_WR_EN */
+#define SOURCE_PIF_PKT_ALLOC_WR_EN 12
+#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_PKT_ALLOC_WR_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_SW_RESET */
+#define SOURCE_PIF_SW_RESET 13
+#define F_SW_RST(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+#endif /*SOURCE_PIF */
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_vif.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_VIF_H_
+#define SOURCE_VIF_H_
+
+/* register BND_HSYNC2VSYNC */
+#define BND_HSYNC2VSYNC 0
+#define F_IP_DTCT_WIN(x) (((x) & ((1 << 12) - 1)) << 0)
+#define F_IP_DTCT_WIN_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0)
+#define F_IP_DET_EN(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_IP_DET_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_IP_VIF_BYPASS(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_IP_VIF_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13)
+
+/* register HSYNC2VSYNC_F1_L1 */
+#define HSYNC2VSYNC_F1_L1 1
+#define F_IP_DTCT_HSYNC2VSYNC_F1(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_IP_DTCT_HSYNC2VSYNC_F1_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+
+/* register HSYNC2VSYNC_F2_L1 */
+#define HSYNC2VSYNC_F2_L1 2
+#define F_IP_DTCT_HSYNC2VSYNC_F2(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_IP_DTCT_HSYNC2VSYNC_F2_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+
+/* register HSYNC2VSYNC_STATUS */
+#define HSYNC2VSYNC_STATUS 3
+#define F_IP_DTCT_ERR(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_IP_DTCT_ERR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_IP_DCT_IP(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_IP_DCT_IP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_IP_DTCT_VJITTER(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_IP_DTCT_VJITTER_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_IP_DTCT_HJITTER(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_IP_DTCT_HJITTER_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register HSYNC2VSYNC_POL_CTRL */
+#define HSYNC2VSYNC_POL_CTRL 4
+#define F_VPOL(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_VPOL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_HPOL(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HPOL_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_VIF_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_VIF_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+#endif /*SOURCE_VIF */
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
unsigned int tmp;
} state_struct;
+extern state_struct state;
+extern int cdn_bus_read(unsigned int addr, unsigned int* value);
+extern int cdn_bus_write(unsigned int addr, unsigned int value);
unsigned short internal_get_msg_len(void);
#endif
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * vic_table.c
+ *
+ ******************************************************************************
+ */
+#include "vic_table.h"
+
+const unsigned int vic_table[VIC_MODE_COUNT][27] = {
+ {858, 720, 138, 62, 16, 60, 525, 480, 45, 6, 9, 30, 59, 27000,
+ PROGRESSIVE, ACTIVE_LOW, ACTIVE_LOW, 1, 65535, 1, 46, 65535, 65535, 3,
+ 8, 0},
+ {1650, 1280, 370, 40, 110, 220, 750, 720, 30, 5, 5, 20, 60, 74250,
+ PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 1, 65535, 1, 31, 65535, 65535,
+ 4, 8, 0},
+ {2200, 1920, 280, 44, 88, 148, 1125, 1080, 45, 5, 4,
+ 36, 60, 148500, PROGRESSIVE, ACTIVE_HIGH,
+ ACTIVE_HIGH, 1, 65535, 1, 46, 65535, 65535, 16, 8, 0},
+ {4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 60,
+ 594000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525,
+ 285, 97, 8, 0},
+ {4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 30,
+ 297000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525,
+ 285, 95, 8, 0},
+};
--- /dev/null
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * vic_table.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef VIC_TABLE_H_
+#define VIC_TABLE_H_
+
+#define PROGRESSIVE 0
+#define INTERLACED 1
+
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+
+typedef enum {
+ H_TOTAL,
+ H_ACTIVE,
+ H_BLANK,
+ HSYNC,
+ FRONT_PORCH,
+ BACK_PORCH,
+ /* H_FREQ_KHZ, */
+ V_TOTAL,
+ V_ACTIVE,
+ V_BLANK,
+ VSYNC,
+ TYPE_EOF,
+ SOF,
+ V_FREQ_HZ,
+ PIXEL_FREQ_KHZ,
+ I_P,
+ HSYNC_POL,
+ VSYNC_POL,
+ START_OF_F0,
+ START_OF_F1,
+ VSYNC_START_INTERLACED_F0,
+ VSYNC_END_INTERLACED_F0,
+ VSYNC_START_INTERLACED_F1,
+ VSYNC_END_INTERLACED_F1,
+ VIC,
+ VIC_R3_0,
+ VIC_PR,
+} MSA_PARAM;
+
+typedef enum {
+ NUM_OF_LANES_1 = 1,
+ NUM_OF_LANES_2 = 2,
+ NUM_OF_LANES_4 = 4,
+} VIC_NUM_OF_LANES;
+
+typedef enum {
+ RATE_1_6 = 162,
+ RATE_2_7 = 270,
+ RATE_5_4 = 540,
+ RATE_8_1 = 810,
+} VIC_SYMBOL_RATE;
+
+typedef enum {
+ PXL_RGB = 0x1,
+ YCBCR_4_4_4 = 0x2,
+ YCBCR_4_2_2 = 0x4,
+ YCBCR_4_2_0 = 0x8,
+ Y_ONLY = 0x10,
+} VIC_PXL_ENCODING_FORMAT;
+
+typedef enum {
+ BCS_6 = 0x1,
+ BCS_8 = 0x2,
+ BCS_10 = 0x4,
+ BCS_12 = 0x8,
+ BCS_16 = 0x10,
+} VIC_COLOR_DEPTH;
+
+typedef enum {
+ STEREO_VIDEO_LEFT = 0x0,
+ STEREO_VIDEO_RIGHT = 0x1,
+} STEREO_VIDEO_ATTR;
+
+typedef enum {
+ BT_601 = 0x0,
+ BT_709 = 0x1,
+} BT_TYPE;
+
+typedef enum {
+ VIC_MODE_3_59_94Hz,
+ VIC_MODE_4_60Hz,
+ VIC_MODE_16_60Hz,
+ VIC_MODE_97_60Hz,
+ VIC_MODE_95_30Hz,
+ VIC_MODE_COUNT
+} VIC_MODES;
+
+extern const unsigned int vic_table[VIC_MODE_COUNT][27];
+
+#endif
--- /dev/null
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/imx-common/video.h>
+#include <asm/arch/video_common.h>
+#include <imx8_hdmi.h>
+
+#include "API_General.h"
+#include "vic_table.h"
+#include "API_HDMITX.h"
+#include "apb_cfg.h"
+#include "externs.h"
+#include "API_AVI.h"
+#include "address.h"
+#include "source_car.h"
+#include "source_phy.h"
+#include "API_AFE.h"
+#include "source_vif.h"
+#include "general_handler.h"
+#include "mhl_hdtx_top.h"
+
+
+#ifdef CONFIG_IMX8QM
+#include "API_AFE_mcu1_dp.h"
+#include "API_AFE_ss28fdsoi_kiran_hdmitx.h"
+#endif
+
+#ifdef CONFIG_IMX8M
+#include "API_AFE_t28hpc_hdmitx.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ON 1
+#define OFF 0
+
+unsigned long g_encoding = 1; /* 1 RGB, 2 YUV 444, 4 YUV 422, 8 YUV 420 */
+unsigned long g_color_depth = 8; /* 8 pits per color */
+
+static int imx8_hdmi_set_vic_mode(int vic,
+ struct video_mode_settings *vms)
+{
+ /*struct video_mode_settings *vms = &vm_settings[VM_USER]; */
+ uint32_t pixel_clock_kHz;
+ uint32_t frame_rate_Hz;
+ uint32_t frame_rate_frac_Hz;
+ uint32_t cea_vic;
+ char iflag;
+
+ if (vic >= VIC_MODE_COUNT) {
+ debug("%s(): unsupported VIC\n", __func__);
+ return -1;
+ }
+
+
+ vms->hfp = vic_table[vic][FRONT_PORCH];
+ vms->hbp = vic_table[vic][BACK_PORCH];
+ vms->hsync = vic_table[vic][HSYNC];
+ vms->vfp = vic_table[vic][TYPE_EOF];
+ vms->vbp = vic_table[vic][SOF];
+ vms->vsync = vic_table[vic][VSYNC];
+ vms->xres = vic_table[vic][H_ACTIVE];
+ vms->yres = vic_table[vic][V_ACTIVE];
+
+ vms->hpol = vic_table[vic][HSYNC_POL] != 0;
+ vms->vpol = vic_table[vic][VSYNC_POL] != 0;
+
+ cea_vic = vic_table[vic][VIC];
+ if (vic_table[vic][I_P] != 0)
+ iflag = 'i';
+ else
+ iflag = 'p';
+ pixel_clock_kHz = vic_table[vic][PIXEL_FREQ_KHZ];
+ frame_rate_Hz = vic_table[vic][V_FREQ_HZ] * 1000;
+ frame_rate_frac_Hz = frame_rate_Hz % 1000;
+ frame_rate_Hz /= 1000;
+
+ vms->pixelclock = pixel_clock_kHz;
+
+ debug("Cadence VIC %3d, CEA VIC %3d: %4d x %4d %c @ %3d.%03d [%6d kHz] Vpol=%d Hpol=%d\n",
+ vic, cea_vic, vms->xres, vms->yres, iflag, frame_rate_Hz,
+ frame_rate_frac_Hz, pixel_clock_kHz, vms->vpol, vms->hpol);
+
+ debug(" mode timing fp sync bp h:%3d %3d %3d v:%3d %3d %3d\n",
+ vms->hfp, vms->hsync, vms->hbp, vms->vfp, vms->vsync, vms->vbp);
+
+ return 0;
+ /*debug("leaving %s() ...\n", __func__); */
+}
+
+static int imx8_hdmi_init(int vic,
+ int encoding,
+ int color_depth,
+ bool pixel_clk_from_phy)
+{
+ int ret;
+#ifdef CONFIG_IMX8QM
+ sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle;
+ void __iomem *hdmi_csr_base = (void __iomem *)0x56261000;
+#endif
+ /*GENERAL_Read_Register_response regresp; */
+ /*uint8_t sts; */
+ uint32_t character_freq_khz;
+
+ uint8_t echo_msg[] = "echo test";
+ uint8_t echo_resp[sizeof(echo_msg) + 1];
+ /*uint8_t response; */
+ /*uint8_t dpcd_resp; */
+ /*uint8_t hdcp_resp; */
+ /*uint8_t capb_resp; */
+ /*uint32_t temp; */
+
+ /*================================================================== */
+ /* Parameterization: */
+ /*================================================================== */
+
+ /* VIC Mode - index from vic_table (see API_SRC/vic_table.c) */
+ VIC_MODES vic_mode = vic;
+
+ /* Pixel Encodeing Format */
+ /* PXL_RGB = 0x1, */
+ /* YCBCR_4_4_4 = 0x2, */
+ /* YCBCR_4_2_2 = 0x4, */
+ /* YCBCR_4_2_0 = 0x8, */
+ /* Y_ONLY = 0x10, */
+ VIC_PXL_ENCODING_FORMAT format = encoding;
+ /*VIC_PXL_ENCODING_FORMAT format = 1; */
+
+ /* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */
+ BT_TYPE bw_type = 0;
+
+ /* bpp (bits per subpixel) - 8 24bpp, 10 30bpp, 12 36bpp, 16 48bpp */
+ uint8_t bps = color_depth;
+
+ /* Set HDMI TX Mode */
+ /* Mode = 0 - DVI, 1 - HDMI1.4, 2 HDMI 2.0 */
+ HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE ptype = 1;
+
+ if (vic_mode == VIC_MODE_97_60Hz)
+ ptype = 2;
+
+ /*================================================================== */
+ /* Parameterization done */
+ /*================================================================== */
+#ifdef CONFIG_IMX8QM
+ /* set the pixel link mode and pixel type */
+ SC_MISC_SET_CONTROL(ipcHndl, SC_R_HDMI, SC_C_PHY_RESET, 0);
+#if 1
+ SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0, SC_C_PXL_LINK_MST1_ADDR, 1);
+ /*SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0, SC_C_PXL_LINK_MST1_ADDR, 0);*/
+ if (g_clock_mode == CLOCK_MODES_HDMI_DUAL) {
+ SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0,
+ SC_C_PXL_LINK_MST2_ADDR, 2);
+ /*SC_MISC_SET_CONTROL(ipcHndl, SC_R_DC_0,
+ SC_C_PXL_LINK_MST2_ADDR, 0); */
+ __raw_writel(0x6, hdmi_csr_base);
+ } else
+#endif
+ __raw_writel(0x34, hdmi_csr_base);
+#endif
+ cdn_api_init();
+ debug("CDN_API_Init completed\n");
+
+ ret = cdn_api_checkalive_blocking();
+ debug("CDN_API_CheckAlive returned ret = %d\n", ret);
+
+ ret = cdn_api_general_test_echo_ext_blocking(echo_msg,
+ echo_resp,
+ sizeof(echo_msg),
+ CDN_BUS_TYPE_APB);
+ debug("_General_Test_Echo_Ext_blocking - (ret = %d echo_resp = %s)\n",
+ ret, echo_resp);
+
+ /* Configure PHY */
+ character_freq_khz = phy_cfg_t28hpc(4, vic_mode, bps,
+ format, pixel_clk_from_phy);
+ debug("phy_cfg_t28hpc (character_freq_mhz = %d)\n",
+ character_freq_khz);
+
+ /*phy_reset(1); */
+
+#ifdef CONFIG_IMX8QM
+ SC_MISC_SET_CONTROL(ipcHndl, SC_R_HDMI, SC_C_PHY_RESET, 1);
+#endif
+ hdmi_tx_t28hpc_power_config_seq(4);
+#ifdef CONFIG_IMX8QM
+ /* Set the lane swapping */
+ ret = cdn_api_general_write_register_blocking
+ (ADDR_SOURCD_PHY + (LANES_CONFIG << 2),
+ F_SOURCE_PHY_LANE0_SWAP(3) | F_SOURCE_PHY_LANE1_SWAP(0) |
+ F_SOURCE_PHY_LANE2_SWAP(1) | F_SOURCE_PHY_LANE3_SWAP(2) |
+ F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1));
+#else
+ /* Set the lane swapping */
+ ret = cdn_api_general_write_register_blocking
+ (ADDR_SOURCD_PHY + (LANES_CONFIG << 2),
+ F_SOURCE_PHY_LANE0_SWAP(0) | F_SOURCE_PHY_LANE1_SWAP(1) |
+ F_SOURCE_PHY_LANE2_SWAP(2) | F_SOURCE_PHY_LANE3_SWAP(3) |
+ F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1));
+#endif
+ debug("_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret);
+
+ ret = CDN_API_HDMITX_Init_blocking();
+ debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret);
+
+ ret = CDN_API_HDMITX_Init_blocking();
+ debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret);
+
+ ret = CDN_API_HDMITX_Set_Mode_blocking(ptype, character_freq_khz);
+ debug("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
+
+ ret = cdn_api_set_avi(vic_mode, format, bw_type);
+ debug("cdn_api_set_avi ret = %d\n", ret);
+
+ ret = CDN_API_HDMITX_SetVic_blocking(vic_mode, bps, format);
+ debug("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
+
+#ifdef CONFIG_IMX8QM
+ {
+ GENERAL_Read_Register_response regresp;
+ /* adjust the vsync/hsync polarity */
+ cdn_api_general_read_register_blocking(ADDR_SOURCE_VIF +
+ (HSYNC2VSYNC_POL_CTRL
+ << 2),
+ ®resp);
+ debug("Initial HSYNC2VSYNC_POL_CTRL: 0x%x\n", regresp.val);
+ if ((regresp.val & 0x3) != 0)
+ __raw_writel(0x4, hdmi_csr_base);
+ }
+#endif
+ /*regresp.val &= ~0x03; // clear HSP and VSP bits */
+ /*debug("Final HSYNC2VSYNC_POL_CTRL: 0x%x\n",regresp.val); */
+ /*CDN_API_General_Write_Register_blocking(ADDR_DPTX_FRAMER +
+ (DP_FRAMER_SP << 2),
+ regresp.val); */
+
+ udelay(20000);
+
+ return 0;
+}
+
+void imx8_hdmi_enable(int encoding,
+ struct video_mode_settings *vms)
+{
+ int vic = 0;
+ const int use_phy_pixel_clk = 1;
+
+ /* map the resolution to a VIC index in the vic table*/
+ if ((vms->xres == 1280) && (vms->yres == 720))
+ vic = 1; /* 720p60 */
+ else if ((vms->xres == 1920) && (vms->yres == 1080))
+ vic = 2; /* 1080p60 */
+ else if ((vms->xres == 3840) && (vms->yres == 2160))
+ vic = 3; /* 2160p60 */
+ else /* if ((vms->xres == 720) && (vms->yres == 480)) */
+ vic = 0; /* 480p60 */
+
+ imx8_hdmi_set_vic_mode(vic, vms);
+ imx8_hdmi_init(vic, encoding, g_color_depth, use_phy_pixel_clk);
+}
+
+void imx8_hdmi_disable(void)
+{
+ int ret;
+ GENERAL_READ_REGISTER_RESPONSE resp;
+
+ resp.val = 0;
+ ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ &resp);
+ if (ret != CDN_OK) {
+ printf("%s(): dn_api_general_read_register_blocking failed\n",
+ __func__);
+ /*return;*/
+ }
+
+ resp.val &= ~F_DATA_EN(1); /* disable HDMI */
+ /*resp.val |= F_SET_AVMUTE( 1);*/
+
+ ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+ (HDTX_CONTROLLER << 2),
+ resp.val);
+ if (ret != CDN_OK) {
+ printf("%s(): dn_api_general_write_register_blocking failed\n",
+ __func__);
+ return;
+ }
+}
projects / u-boot.git / commitdiff