MLK-9920 mtd: fsl-quadspi: Add ddrsmp parameter to device tree

Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for different i.MX6SX board.

Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked and merge from commit c9115cc22d836b5b980ca20932a005ea61b20082)
(cherry picked from commit b0d9d9ce804247ccb2842bf53d2b32f14eed0309)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 6e881bd..0a1f864 100644 (file)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -288,6 +288,7 @@ struct fsl_qspi {
        unsigned int chip_base_addr; /* We may support two chips. */
        bool has_second_chip;
        bool big_endian;
+       u32 ddr_smp;
        struct mutex lock;
        struct pm_qos_request pm_qos_req;
 };
@@ -742,7 +743,8 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
                /* Set the Sampling Register for DDR */
                reg2 = readl(q->iobase + QUADSPI_SMPR);
                reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
-               reg2 |= (2 << QUADSPI_SMPR_DDRSMP_SHIFT);
+               reg2 |= ((q->ddr_smp << QUADSPI_SMPR_DDRSMP_SHIFT) &
+                        QUADSPI_SMPR_DDRSMP_MASK);
                qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
 
                /* Enable the module again (enable the DDR too) */
@@ -1069,6 +1071,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
        if (IS_ERR(q->clk))
                return PTR_ERR(q->clk);
 
+       /* find ddrsmp value */
+       ret = of_property_read_u32(dev->of_node, "ddrsmp",
+                               &q->ddr_smp);
+       if (ret)
+               q->ddr_smp = 0;
+
        ret = fsl_qspi_clk_prep_enable(q);
        if (ret) {
                dev_err(dev, "can not enable the clock\n");