MLK-14973 arm64: dts: imx8qm: add DMA subsystem UART ports and DMA chans

Add DMA subsystem UART ports and related DMA channels for i.MX8QM
lpddr4 arm2 board.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index 5038504..953c119 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -92,6 +92,22 @@
                        >;
                };
 
+               pinctrl_lpuart1: lpuart1grp {
+                       fsl,pins = <
+                               SC_P_UART1_RX_DMA_UART1_RX              0x0600004c
+                               SC_P_UART1_TX_DMA_UART1_TX              0x0600004c
+                               SC_P_UART1_CTS_B_DMA_UART1_CTS_B        0x0600004c
+                               SC_P_UART1_RTS_B_DMA_UART1_RTS_B        0x0600004c
+                       >;
+               };
+
+               pinctrl_lpuart3: lpuart3grp {
+                       fsl,pins = <
+                               SC_P_M41_GPIO0_00_DMA_UART3_RX          0x0600004c
+                               SC_P_M41_GPIO0_01_DMA_UART3_TX          0x0600004c
+                       >;
+               };
+
                pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
                                SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000021
@@ -314,13 +330,21 @@
        };
 };
 
-&lpuart0 {
+&lpuart0 { /* console */
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lpuart0>;
        status = "okay";
 };
 
-&lpuart1 {
+&lpuart1 { /* BT */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart1>;
+       status = "okay";
+};
+
+&lpuart3 { /* GPS */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart3>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 686bbe7..9cd3068 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -33,6 +33,9 @@
                ethernet2 = &fec2;
                serial0 = &lpuart0;
                serial1 = &lpuart1;
+               serial2 = &lpuart2;
+               serial3 = &lpuart3;
+               serial4 = &lpuart4;
                mmc0 = &usdhc1;
                mmc1 = &usdhc2;
                mmc2 = &usdhc3;
@@ -1014,20 +1017,6 @@
                status = "disabled";
        };
 
-       lpuart0: serial@5a060000 {
-               compatible = "fsl,imx8qm-lpuart";
-               reg = <0x0 0x5a060000 0x0 0x1000>;
-               interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-parent = <&gic>;
-               clocks = <&clk IMX8QM_UART0_CLK>,
-                        <&clk IMX8QM_UART0_IPG_CLK>;
-               clock-names = "per", "ipg";
-               assigned-clock-names = <&clk IMX8QM_UART0_CLK>;
-               assigned-clock-rates = <80000000>;
-               power-domains = <&pd_dma_lpuart0>;
-               status = "disabled";
-       };
-
        lpspi0: lpspi@5a000000 {
                compatible = "fsl,imx7ulp-spi";
                reg = <0x0 0x5a000000 0x0 0x10000>;
@@ -1041,6 +1030,20 @@
                status = "disabled";
        };
 
+       lpuart0: serial@5a060000 {
+               compatible = "fsl,imx8qm-lpuart";
+               reg = <0x0 0x5a060000 0x0 0x1000>;
+               interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_UART0_CLK>,
+                        <&clk IMX8QM_UART0_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_UART0_CLK>;
+               assigned-clock-rates = <80000000>;
+               power-domains = <&pd_dma_lpuart0>;
+               status = "disabled";
+       };
+
        lpuart1: serial@5a070000 {
                compatible = "fsl,imx8qm-lpuart";
                reg = <0x0 0x5a070000 0x0 0x1000>;
@@ -1049,7 +1052,7 @@
                clocks = <&clk IMX8QM_UART1_CLK>,
                        <&clk IMX8QM_UART1_IPG_CLK>;
                clock-names = "per", "ipg";
-               assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
+               assigned-clocks = <&clk IMX8QM_UART1_CLK>;
                assigned-clock-rates = <80000000>;
                power-domains = <&pd_dma_lpuart1>;
                dma-names = "tx","rx";
@@ -1058,20 +1061,86 @@
                status = "disabled";
        };
 
+       lpuart2: serial@5a080000 {
+               compatible = "fsl,imx8qm-lpuart";
+               reg = <0x0 0x5a080000 0x0 0x1000>;
+               interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_UART2_CLK>,
+                       <&clk IMX8QM_UART2_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_UART2_CLK>;
+               assigned-clock-rates = <80000000>;
+               power-domains = <&pd_dma_lpuart2>;
+               dma-names = "tx","rx";
+               dmas = <&edma0 17 0 0>,
+                       <&edma0 16 0 1>;
+               status = "disabled";
+       };
+
+       lpuart3: serial@5a090000 {
+               compatible = "fsl,imx8qm-lpuart";
+               reg = <0x0 0x5a090000 0x0 0x1000>;
+               interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_UART3_CLK>,
+                       <&clk IMX8QM_UART3_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_UART3_CLK>;
+               assigned-clock-rates = <80000000>;
+               power-domains = <&pd_dma_lpuart3>;
+               dma-names = "tx","rx";
+               dmas = <&edma0 19 0 0>,
+                       <&edma0 18 0 1>;
+               status = "disabled";
+       };
+
+       lpuart4: serial@5a0a0000 {
+               compatible = "fsl,imx8qm-lpuart";
+               reg = <0x0 0x5a0a0000 0x0 0x1000>;
+               interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_UART4_CLK>,
+                       <&clk IMX8QM_UART4_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_UART4_CLK>;
+               assigned-clock-rates = <80000000>;
+               power-domains = <&pd_dma_lpuart4>;
+               dma-names = "tx","rx";
+               dmas = <&edma0 21 0 0>,
+                       <&edma0 20 0 1>;
+               status = "disabled";
+       };
+
        edma0: dma-controller@40018000 {
                compatible = "fsl,imx8qm-edma";
                reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
                      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
                      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
-                     <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
+                     <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */
+                     <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */
+                     <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */
+                     <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */
+                     <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */
+                     <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
+                     <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
                #dma-cells = <3>;
-               dma-channels = <4>;
+               dma-channels = <10>;
                interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
+                            <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "edma-chan12-tx", "edma-chan13-tx",
-                                 "edma-chan14-tx", "edma-chan15-tx";
+                                 "edma-chan14-tx", "edma-chan15-tx",
+                                 "edma-chan16-tx", "edma-chan17-tx",
+                                 "edma-chan18-tx", "edma-chan19-tx",
+                                 "edma-chan20-tx", "edma-chan21-tx";
                status = "okay";
        };