MLK-13642 ARM: imx: update the ddr frequency change flow on imx7d

Update busfreq change flow on i.MX7D. When changing the
DDR frequency to 24MHz, 98MHz and 533MHz, different value
should be set in 'DDRC_RFSHTMG' register. Detailed setting
is below:

LPDDR2/3:
    24MHz:  0x00010003
    98MHz:  0x0005000B
    533MHz: 0x00200038

DDR3:
    24MHz:  0x00030004
    98MHz:  0x000B000D
    533MHz: 0x00040046

Signed-off-by: Bai Ping <ping.bai@nxp.com>

diff --git a/arch/arm/mach-imx/ddr3_freq_imx7d.S b/arch/arm/mach-imx/ddr3_freq_imx7d.S
index ff767c0..9342e0d 100644 (file)
--- a/arch/arm/mach-imx/ddr3_freq_imx7d.S
+++ b/arch/arm/mach-imx/ddr3_freq_imx7d.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@
 #define DDRC_MRSTAT            0x18
 #define DDRC_PWRCTL            0x30
 #define DDRC_RFSHCTL3          0x60
+#define DDRC_RFSHTMG           0x64
 #define DDRC_DBG1              0x304
 #define DDRC_SWCTL             0x320
 #define DDRC_SWSTAT            0x324
@@ -135,7 +136,15 @@
 
        ldr     r6, =24000000
        cmp     r0, r6
-       bne     7f
+       beq     25f
+
+       ldr     r7, =0x000B000D
+       str     r7,[r4, #DDRC_RFSHTMG]
+       b       7f
+
+25:
+       ldr     r7, =0x00030004
+       str     r7,[r4, #DDRC_RFSHTMG]
 
        /* dram alt sel set to OSC */
        ldr     r7, =0x10000000
@@ -286,6 +295,9 @@
        ldr     r7, =0x10210100
        str     r7, [r5, #0x4]
 
+       ldr     r7, =0x00040046
+       str     r7, [r4, #DDRC_RFSHTMG]
+
        /* dram root set to from dram main, div by 2 */
        ldr     r7, =0x10000001
        ldr     r8, =0x9880

diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S
index 71b4e23..80fb118 100644 (file)
--- a/arch/arm/mach-imx/lpddr3_freq_imx.S
+++ b/arch/arm/mach-imx/lpddr3_freq_imx.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,6 +18,7 @@
 #define DDRC_MSTR              0x0
 #define DDRC_STAT              0x4
 #define DDRC_PWRCTL            0x30
+#define DDRC_RFSHTMG           0x64
 #define DDRC_DBG1              0x304
 #define DDRC_PSTAT             0x3fc
 #define DDRC_PCTRL_0           0x490
@@ -140,12 +141,16 @@
        ldr     r7, =0x10010100
        str     r7, [r5, #DDRPHY_PHY_CON1]
 10:
-       ldr     r7, =0x00020038
-       str     r7, [r5, #DDRPHY_RFSHTMG]
-
        ldr     r6, =24000000
        cmp     r0, r6
-       bne     6f
+       beq     16f
+
+       ldr     r7, =0x0005000B
+       str     r7, [r4, #DDRC_RFSHTMG]
+       b       6f
+16:
+       ldr     r7, =0x00010003
+       str     r7, [r4, #DDRC_RFSHTMG]
 
        /* dram alt sel set to OSC */
        ldr     r7, =0x10000000
@@ -217,7 +222,7 @@
        str     r7, [r5, #DDRPHY_PHY_CON1]
 
        ldr     r7, =0x00200038
-       str     r7, [r5, #DDRPHY_RFSHTMG]
+       str     r7, [r4, #DDRC_RFSHTMG]
 
        /* dram root set to from dram main, div by 2 */
        ldr     r7, =0x10000001