MLK-15350 ARM64: dts: fsl-imx8mq-evk: add SD3.0 support

Add SD3.0 and eMMC HS400 support for imx8mq-evk.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
index 86b6cb0..eee97e8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
@@ -29,6 +29,21 @@
                stdout-path = &uart1;
        };
 
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               reg_usdhc2_vmmc: usdhc2_vmmc {
+                       compatible = "regulator-fixed";
+                       regulator-name = "VSD_3V3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+       };
+
        modem_reset: modem-reset {
                compatible = "gpio-reset";
                reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
@@ -145,13 +160,95 @@
 
                pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
-                               MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK         0xd6
+                               MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x81
+                               MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc1
+                               MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc1
+                               MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc1
+                               MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc1
+                               MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc1
+                               MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc1
+                               MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc1
+                               MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc1
+                               MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc1
+                               MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x81
+                               MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
+                       >;
+               };
+
+               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x85
+                               MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc5
+                               MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc5
+                               MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc5
+                               MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc5
+                               MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc5
+                               MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc5
+                               MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc5
+                               MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc5
+                               MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc5
+                               MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x85
+                               MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
+                       >;
+               };
+
+               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x87
+                               MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc7
+                               MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc7
+                               MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc7
+                               MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc7
+                               MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc7
+                               MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc7
+                               MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc7
+                               MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc7
+                               MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc7
+                               MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x87
+                               MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
+                       >;
+               };
+
+               pinctrl_usdhc2_gpio: usdhc2grpgpio {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41
+                               MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
                        >;
                };
 
                pinctrl_usdhc2: usdhc2grp {
                        fsl,pins = <
-                               MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12        0x16
+                               MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x81
+                               MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc1
+                               MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc1
+                               MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc1
+                               MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc1
+                               MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc1
+                               MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
+                       >;
+               };
+
+               pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
+                               MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
+                               MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
+                               MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
+                               MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
+                               MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
+                               MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
+                       >;
+               };
+
+               pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
+                               MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
+                               MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
+                               MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
+                               MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
+                               MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
+                               MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
                        >;
                };
 
@@ -394,18 +491,23 @@
 };
 
 &usdhc1 {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
        bus-width = <8>;
        non-removable;
        status = "okay";
 };
 
 &usdhc2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc2>;
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
        bus-width = <4>;
        cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index d455891..bb5a29d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -528,13 +528,15 @@
        };
 
        usdhc1: usdhc@30b40000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx6sl-usdhc";
+               compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
                reg = <0x0 0x30b40000 0x0 0x10000>;
                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MQ_CLK_DUMMY>,
                        <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
                        <&clk IMX8MQ_CLK_USDHC1_ROOT>;
                clock-names = "ipg", "ahb", "per";
+               assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
+               assigned-clock-rates = <400000000>;
                fsl,tuning-start-tap = <20>;
                fsl,tuning-step= <2>;
                bus-width = <4>;
@@ -542,7 +544,7 @@
        };
 
        usdhc2: usdhc@30b50000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx6sl-usdhc";
+               compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
                reg = <0x0 0x30b50000 0x0 0x10000>;
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MQ_CLK_DUMMY>,