arm64: dts: imx8mn: add display devices nodes

Add LCDIF, MIPI DSI, display subystem display devices
and the required resets nodes.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 5852019..9a5969f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -301,6 +301,47 @@
                arm,no-tick-in-suspend;
        };
 
+       lcdif_resets: lcdif-resets {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               #reset-cells = <0>;
+
+               lcdif-soft-resetn {
+                       compatible = "lcdif,soft-resetn";
+                       resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>,
+                                <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>;
+               };
+
+               lcdif-clk-enable {
+                       compatible = "lcdif,clk-enable";
+                       resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>,
+                                <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>;
+               };
+       };
+
+       mipi_dsi_resets: mipi-dsi-resets {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               #reset-cells = <0>;
+
+               dsi-soft-resetn {
+                       compatible = "dsi,soft-resetn";
+                       resets = <&dispmix_sft_rstn IMX8MN_MIPI_DSI_CLKREF_RESET>,
+                                <&dispmix_sft_rstn IMX8MN_MIPI_DSI_PCLK_RESET>;
+               };
+
+               dsi-clk-enable {
+                       compatible = "dsi,clk-enable";
+                       resets = <&dispmix_clk_en IMX8MN_MIPI_DSI_CLKREF_EN>,
+                                <&dispmix_clk_en IMX8MN_MIPI_DSI_PCLK_EN>;
+               };
+
+               dsi-mipi-reset {
+                       compatible = "dsi,mipi-reset";
+                       resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>;
+               };
+       };
+
        isi_resets: isi-resets {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -1107,6 +1148,69 @@
                        #size-cells = <1>;
                        ranges;
 
+                       lcdif: lcd-controller@32e00000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx8mn-lcdif";
+                               reg = <0x32e00000 0x10000>;
+                               clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+                               clock-names = "pix", "disp-axi", "disp-apb";
+                               assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
+                                                 <&clk IMX8MN_CLK_DISP_AXI>,
+                                                 <&clk IMX8MN_CLK_DISP_APB>;
+                               assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>,
+                                                        <&clk IMX8MN_SYS_PLL2_1000M>,
+                                                        <&clk IMX8MN_SYS_PLL1_800M>;
+                               assigned-clock-rate = <594000000>,
+                                                     <500000000>,
+                                                     <200000000>;
+                               interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                               resets = <&lcdif_resets>;
+                               power-domains = <&dispmix_pd>;
+                               status = "disabled";
+
+                               lcdif_disp0: port@0 {
+                                       reg = <0>;
+
+                                       lcdif_to_dsim: endpoint {
+                                               remote-endpoint = <&dsim_from_lcdif>;
+                                       };
+                               };
+                       };
+
+                       mipi_dsi: dsi_controller@32e10000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx8mn-mipi-dsim";
+                               reg = <0x32e10000 0x400>;
+                               clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+                                        <&clk IMX8MN_CLK_DSI_PHY_REF>;
+                               clock-names = "cfg", "pll-ref";
+                               assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+                                                 <&clk IMX8MN_CLK_DSI_PHY_REF>;
+                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+                                                        <&clk IMX8MN_VIDEO_PLL1_OUT>;
+                               assigned-clock-rates = <266000000>,
+                                                      <594000000>;
+                               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                               resets = <&mipi_dsi_resets>;
+                               power-domains = <&mipi_pd>;
+                               status = "disabled";
+
+                               port@0 {
+                                       dsim_from_lcdif: endpoint {
+                                               remote-endpoint = <&lcdif_to_dsim>;
+                                       };
+                               };
+                       };
+
+                       display-subsystem {
+                               compatible = "fsl,imx-display-subsystem";
+                               ports = <&lcdif_disp0>;
+                       };
+
                        usbotg1: usb@32e40000 {
                                compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
                                reg = <0x32e40000 0x200>;