MLK-14525: ASoC: fsl_esai: channel swap issue in 3 channels or 5 channels

In 3 channels, ESAI is set to I2S mode and two dataline, so actually
ESAI is working in 4 channels mode, (we can't get correct 3 channels,
for we can't make one dataline working in 2 channel, another dataline
working in 1 channels).

In this case, we fill channels (3) zero data to FIFO in start phase,
which should cause channel swap, that we need to fill 4 zero data to
FIFO for ESAI working in 4 channels mode actually.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>

diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 4e2b3c0..204e431 100644 (file)
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -2,6 +2,7 @@
  * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
  *
  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
@@ -596,7 +597,7 @@ static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
                                   ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
 
                /* Write initial words reqiured by ESAI as normal procedure */
-               for (i = 0; tx && i < channels; i++)
+               for (i = 0; tx && i < pins * esai_priv->slots; i++)
                        regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
 
                regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),