MLK-15298 imx8mq: reuse imx-common code to add reset cause

Reuse imx-common code for cpuinfo.
Add a dummy crm_regs.h file, becasue imx-common code includes it.
Add src register map for i.MX8M.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/cpu/armv8/imx8m/soc.c b/arch/arm/cpu/armv8/imx8m/soc.c
index 276fb47..c26c97e 100644 (file)
--- a/arch/arm/cpu/armv8/imx8m/soc.c
+++ b/arch/arm/cpu/armv8/imx8m/soc.c
@@ -81,44 +81,9 @@ struct mm_region *mem_map = imx8m_mem_map;
 u32 get_cpu_rev(void)
 {
        /* TODO: */
-       return (MXC_CPU_IMX8MQ << 12) | (0 << 4);
+       return (MXC_CPU_IMX8MQ << 12) | (1 << 4);
 }
 
-#ifdef CONFIG_DISPLAY_CPUINFO
-const char *get_imx8m_type(u32 imxtype)
-{
-       switch (imxtype) {
-       case MXC_CPU_IMX8MQ:
-               return "8MQ";   /* i.MX8 Quad MAX */
-       default:
-               return "??";
-       }
-}
-
-const char *get_imx8m_rev(u32 rev)
-{
-       switch (rev) {
-       case CHIP_REV_A:
-               return "A";
-       default:
-               return "?";
-       }
-}
-
-int print_cpuinfo(void)
-{
-       u32 cpurev;
-       cpurev = get_cpu_rev();
-
-       printf("CPU:   i.MX%s rev%s at %d MHz\n",
-              get_imx8m_type((cpurev & 0xFF000) >> 12),
-              get_imx8m_rev((cpurev & 0xFFF)),
-              mxc_get_clock(MXC_ARM_CLK) / 1000000);
-
-       return 0;
-}
-#endif
-
 int arch_cpu_init(void)
 {
        /*

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 43ce117..7e3b303 100644 (file)
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -13,6 +13,7 @@ endif
 ifeq ($(SOC),$(filter $(SOC),imx8m))
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-y += cpu.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 obj-y  += cpu.o speed.o

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index b4c0492..404f5cd 100644 (file)
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -4,6 +4,8 @@
  *
  * (C) Copyright 2009-2016 Freescale Semiconductor, Inc.
  *
+ * Copyright 2017 NXP
+ *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
@@ -66,6 +68,11 @@ static char *get_reset_cause(void)
                return "WDOG4";
        case 0x00200:
                return "TEMPSENSE";
+#elif defined(CONFIG_IMX8M)
+       case 0x00100:
+               return "WDOG2";
+       case 0x00200:
+               return "TEMPSENSE";
 #else
        case 0x00100:
                return "TEMPSENSE";
@@ -141,6 +148,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
        switch (imxtype) {
+       case MXC_CPU_IMX8MQ:
+               return "8MQ";   /* Quad-core version of the imx8m */
        case MXC_CPU_MX7S:
                return "7S";    /* Single-core version of the mx7 */
        case MXC_CPU_MX7D:
@@ -276,7 +285,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifndef CONFIG_MX7
+#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 u32 get_ahb_clk(void)
 {
        struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -314,6 +323,7 @@ void arch_preboot_os(void)
 #endif
 }
 
+#ifndef CONFIG_IMX8M
 void set_chipselect_size(int const cs_size)
 {
        unsigned int reg;
@@ -344,3 +354,4 @@ void set_chipselect_size(int const cs_size)
 
        writel(reg, &iomuxc_regs->gpr[1]);
 }
+#endif

diff --git a/arch/arm/include/asm/arch-imx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h
new file mode 100644 (file)
index 0000000..997e97a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/crm_regs.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
+#define _ASM_ARCH_IMX8M_CRM_REGS_H
+/* Dummy header, some imx-common code needs this file */
+#endif

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b99dfda..bdee47f 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -192,6 +192,47 @@ struct fuse_bank9_regs {
        u32 rsvd1[11];
 };
 
+/* System Reset Controller (SRC) */
+struct src {
+       u32 scr;
+       u32 a53rcr;
+       u32 a53rcr1;
+       u32 m4rcr;
+       u32 reserved1[4];
+       u32 usbophy1_rcr;
+       u32 usbophy2_rcr;
+       u32 mipiphy_rcr;
+       u32 pciephy_rcr;
+       u32 hdmi_rcr;
+       u32 disp_rcr;
+       u32 reserved2[2];
+       u32 gpu_rcr;
+       u32 vpu_rcr;
+       u32 pcie2_rcr;
+       u32 mipiphy1_rcr;
+       u32 mipiphy2_rcr;
+       u32 reserved3;
+       u32 sbmr1;
+       u32 srsr;
+       u32 reserved4[2];
+       u32 sisr;
+       u32 simr;
+       u32 sbmr2;
+       u32 gpr1;
+       u32 gpr2;
+       u32 gpr3;
+       u32 gpr4;
+       u32 gpr5;
+       u32 gpr6;
+       u32 gpr7;
+       u32 gpr8;
+       u32 gpr9;
+       u32 gpr10;
+       u32 reserved5[985];
+       u32 ddr1_rcr;
+       u32 ddr2_rcr;
+};
+
 #endif
 
 #endif /* __ASM_ARCH_MSCALE_REGS_H__ */