arm64: dts: imx8mq: move watchdog nodes to correct location

The were added at the end of the AIPS1 address space, while they
are in fact in the middle.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 8e9d6d5..a55b932 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -199,6 +199,30 @@
                                #interrupt-cells = <2>;
                        };
 
+                       wdog1: watchdog@30280000 {
+                               compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+                               reg = <0x30280000 0x10000>;
+                               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
+                               status = "disabled";
+                       };
+
+                       wdog2: watchdog@30290000 {
+                               compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+                               reg = <0x30290000 0x10000>;
+                               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
+                               status = "disabled";
+                       };
+
+                       wdog3: watchdog@302a0000 {
+                               compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+                               reg = <0x302a0000 0x10000>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
+                               status = "disabled";
+                       };
+
                        iomuxc: iomuxc@30330000 {
                                compatible = "fsl,imx8mq-iomuxc";
                                reg = <0x30330000 0x10000>;
@@ -228,30 +252,6 @@
                                              "clk_ext1", "clk_ext2",
                                              "clk_ext3", "clk_ext4";
                        };
-
-                       wdog1: watchdog@30280000 {
-                               compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
-                               reg = <0x30280000 0x10000>;
-                               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
-                               status = "disabled";
-                       };
-
-                       wdog2: watchdog@30290000 {
-                               compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
-                               reg = <0x30290000 0x10000>;
-                               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
-                               status = "disabled";
-                       };
-
-                       wdog3: watchdog@302a0000 {
-                               compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
-                               reg = <0x302a0000 0x10000>;
-                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
-                               status = "disabled";
-                       };
                };
 
                bus@30400000 { /* AIPS2 */