MLK-15949-3 ARM64: dts: fsl-imx8qm: correct USDHC per clock rate

Set USDHC2/3 per clock's parent clock to 200MHz.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 4c11123..d8c62cf 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -2026,7 +2026,8 @@
                        <&clk IMX8QM_SDHC1_CLK>,
                        <&clk IMX8QM_CLK_DUMMY>;
                clock-names = "ipg", "per", "ahb";
-               assigned-clock-rates = <400000000>, <200000000>, <0>;
+               assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
+               assigned-clock-rates = <200000000>;
                power-domains = <&pd_conn_sdch1>;
                fsl,tuning-start-tap = <20>;
                fsl,tuning-step= <2>;
@@ -2042,7 +2043,8 @@
                        <&clk IMX8QM_SDHC2_CLK>,
                        <&clk IMX8QM_CLK_DUMMY>;
                clock-names = "ipg", "per", "ahb";
-               assigned-clock-rates = <400000000>, <200000000>, <0>;
+               assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
+               assigned-clock-rates = <200000000>;
                power-domains = <&pd_conn_sdch2>;
                status = "disabled";
        };