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MGS-3786 [#ccc] Cncrease the clock rate of GPU3D/GPU2D for 7ulp B0 board
author
Yuchou Gan
<yuchou.gan@nxp.com>
Fri, 30 Mar 2018 17:45:52 +0000
(
01:45
+0800)
committer
Haibo Chen
<haibo.chen@nxp.com>
Thu, 12 Apr 2018 10:46:38 +0000
(18:46 +0800)
The gpu3d/2d clock rate for 7ulp B0 board is 400M, increase it
Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
(cherry picked from commit
b51ae7e98ccfd9e25697d3e5b9795699917496ea
)
drivers/clk/imx/clk-imx7ulp.c
patch
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diff --git
a/drivers/clk/imx/clk-imx7ulp.c
b/drivers/clk/imx/clk-imx7ulp.c
index
a2853b5
..
6eb9b8f
100644
(file)
--- a/
drivers/clk/imx/clk-imx7ulp.c
+++ b/
drivers/clk/imx/clk-imx7ulp.c
@@
-208,7
+208,7
@@
static void __init imx7ulp_clocks_init(struct device_node *scg_node)
imx_clk_set_parent(clks[IMX7ULP_CLK_GPU2D], clks[IMX7ULP_CLK_APLL_PFD2]);
imx_clk_set_parent(clks[IMX7ULP_CLK_GPU3D], clks[IMX7ULP_CLK_APLL_PFD2]);
- imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2],
35
0000000);
+ imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2],
40
0000000);
/* setting the rate for emmc/sd usage */
imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD1], 352800000);