imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \
imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \
imx8qxp-lpddr4-val-mlb.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-mek-rpmsg.dts"
+
+/ {
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ stdout-path = &lpuart0;
+
+ module@0 {
+ bootargs = "earlycon=xen console=hvc0 root=/dev/mmcblk1p2 rootwait rw";
+ compatible = "xen,linux-zimage", "xen,multiboot-module";
+ /* The size will be override by uboot command */
+ reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>;
+ };
+
+ };
+
+ reserved-memory {
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x30000000>;
+ alloc-ranges = <0 0xb0000000 0 0x40000000>;
+ linux,cma-default;
+ };
+ };
+
+ rtc0: rtc@23000000 {
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ xen,passthrough;
+ };
+};
+
+&imx8_gpu_ss {
+ reg = <0xa8000000 0x58000000>, <0x0 0x10000000>;
+ status = "okay";
+};
+
+&lsio_mu1 {
+ /* not map for dom0, dom0 will mmio trap to xen */
+ xen,no-map;
+};