imx8mn-somdevices: Enable ethernet.
authorJosep Orga <jorga@somdevices.com>
Thu, 7 Oct 2021 16:20:40 +0000 (18:20 +0200)
committerJosep Orga <jorga@somdevices.com>
Thu, 7 Oct 2021 16:20:40 +0000 (18:20 +0200)
Signed-off-by: Josep Orga <jorga@somdevices.com>
arch/arm/dts/imx8mn-somdevices.dts
include/configs/imx8mn_somdevices.h

index 230c1cd..f05ea52 100644 (file)
        pinctrl-0 = <&pinctrl_fec1>;
        phy-mode = "rgmii-id";
        phy-handle = <&ethphy0>;
+       phy-reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+       phy-reset-post-delay = <150>;
+       phy-reset-duration = <10>;
        fsl,magic-packet;
        status = "okay";
 
                #address-cells = <1>;
                #size-cells = <0>;
 
-               ethphy0: ethernet-phy@0 {
+               ethphy0: ethernet-phy@4 {
                        compatible = "ethernet-phy-ieee802.3-c22";
-                       reg = <0>;
+                       reg = <4>;
                };
        };
 };
                        MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
                        MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
                        MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
-                       MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
+                       MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29       0x19
                >;
        };
 
index c49584b..5f1e1b3 100644 (file)
@@ -57,7 +57,7 @@
 #define PHY_ANEG_TIMEOUT 20000
 
 #define CONFIG_FEC_XCV_TYPE             RGMII
-#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_FEC_MXC_PHYADDR          4
 
 #define IMX_FEC_BASE                   0x30BE0000
 #endif