MLK-16359-1: Added i.MX8 CAST IP JPEG Encoder/Decoder Linux to DTS

Adds device tree files for JPEG decoder and encoder to device tree.

Signed-off-by: Zhengyu Shen <zhengyu.shen_1@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 50a3a77..f68c4df 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -952,6 +952,18 @@
                                #power-domain-cells = <0>;
                                power-domains =<&pd_isi_ch0>;
                        };
+
+                       pd_jpgdec: PD_IMAGING_JPEG_DEC {
+                               reg = <SC_R_MJPEG_DEC_S0>;
+                               #power-domain-cells = <0>;
+                               power-domains =<&pd_isi_ch0>;
+                       };
+
+                       pd_jpgenc: PD_IMAGING_JPEG_ENC {
+                               reg = <SC_R_MJPEG_ENC_S0>;
+                               #power-domain-cells = <0>;
+                               power-domains =<&pd_isi_ch0>;
+                       };
                };
        };
 
@@ -1476,6 +1488,32 @@
                        power-domains = <&pd_csi1>;
                        status = "disabled";
                };
+
+               jpegdec: jpegdec@58400000 {
+                       compatible = "fsl,imx8-jpgdec";
+                       reg = <0x0 0x58400000 0x0 0x00040020 >;
+                       interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >,
+                                       <&clk IMX8QM_IMG_JPEG_DEC_CLK >;
+                       clock-names = "ipg", "per";
+                       assigned-clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >,
+                                               <&clk IMX8QM_IMG_JPEG_DEC_CLK >;
+                       assigned-clock-rates = <200000000>;
+                       power-domains =<&pd_jpgdec>;
+               };
+
+               jpegenc: jpegenc@58450000 {
+                       compatible = "fsl,imx8-jpgenc";
+                       reg = <0x0 0x58450000 0x0 0x00240020 >;
+                       interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >,
+                                       <&clk IMX8QM_IMG_JPEG_ENC_CLK >;
+                       clock-names = "ipg", "per";
+                       assigned-clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >,
+                                               <&clk IMX8QM_IMG_JPEG_ENC_CLK >;
+                       assigned-clock-rates = <200000000>;
+                       power-domains =<&pd_jpgenc>;
+               };
        };
 
        i2c0: i2c@5a800000 {