mac[5] = val2 >> 8;
}
+#ifdef CONFIG_IMX_BOOTAUX
+
+#ifdef CONFIG_IMX8QM
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+ sc_ipc_t ipcHndl;
+ sc_rsrc_t core_rsrc, mu_rsrc;
+ sc_faddr_t tcml_addr;
+ u32 tcml_size = SZ_128K;
+ ulong addr;
+
+ ipcHndl = gd->arch.ipc_channel_handle;
+
+ switch (core_id) {
+ case 0:
+ core_rsrc = SC_R_M4_0_PID0;
+ tcml_addr = 0x34FE0000;
+ mu_rsrc = SC_R_M4_0_MU_1A;
+ break;
+ case 1:
+ core_rsrc = SC_R_M4_1_PID0;
+ tcml_addr = 0x38FE0000;
+ mu_rsrc = SC_R_M4_1_MU_1A;
+ break;
+ default:
+ printf("Not support this core boot up, ID:%u\n", core_id);
+ return -EINVAL;
+ }
+
+ addr = (sc_faddr_t)boot_private_data;
+
+ if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
+ printf("Wrong image address 0x%lx, should not in TCML\n",
+ addr);
+ return -EINVAL;
+ }
+
+ printf("Power on M4 and MU\n");
+
+ if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ return -EIO;
+
+ if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ return -EIO;
+
+ printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
+
+ if (addr != tcml_addr)
+ memcpy((void *)tcml_addr, (void *)addr, tcml_size);
+
+ printf("Start M4 %u\n", core_id);
+ if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
+ return -EIO;
+
+ printf("bootaux complete\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_IMX8QXP
+static unsigned long load_elf_image_shdr(unsigned long addr)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf32_Shdr *shdr; /* Section header structure pointer */
+ unsigned char *strtab = 0; /* String table pointer */
+ unsigned char *image; /* Binary image pointer */
+ int i; /* Loop counter */
+
+ ehdr = (Elf32_Ehdr *)addr;
+
+ /* Find the section header string table for output info */
+ shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
+ (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
+
+ if (shdr->sh_type == SHT_STRTAB)
+ strtab = (unsigned char *)(addr + shdr->sh_offset);
+
+ /* Load each appropriate section */
+ for (i = 0; i < ehdr->e_shnum; ++i) {
+ shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
+ (i * sizeof(Elf32_Shdr)));
+
+ if (!(shdr->sh_flags & SHF_ALLOC) ||
+ shdr->sh_addr == 0 || shdr->sh_size == 0) {
+ continue;
+ }
+
+ if (strtab) {
+ debug("%sing %s @ 0x%08lx (%ld bytes)\n",
+ (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
+ &strtab[shdr->sh_name],
+ (unsigned long)shdr->sh_addr,
+ (long)shdr->sh_size);
+ }
+
+ if (shdr->sh_type == SHT_NOBITS) {
+ memset((void *)(uintptr_t)shdr->sh_addr, 0,
+ shdr->sh_size);
+ } else {
+ image = (unsigned char *)addr + shdr->sh_offset;
+ memcpy((void *)(uintptr_t)shdr->sh_addr,
+ (const void *)image, shdr->sh_size);
+ }
+ flush_cache(shdr->sh_addr, shdr->sh_size);
+ }
+
+ return ehdr->e_entry;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+ sc_ipc_t ipcHndl;
+ sc_rsrc_t core_rsrc, mu_rsrc = -1;
+ sc_faddr_t aux_core_ram;
+ u32 size;
+ ulong addr;
+
+ ipcHndl = gd->arch.ipc_channel_handle;
+
+ switch (core_id) {
+ case 0:
+ core_rsrc = SC_R_M4_0_PID0;
+ aux_core_ram = 0x34FE0000;
+ mu_rsrc = SC_R_M4_0_MU_1A;
+ size = SZ_128K;
+ break;
+ case 1:
+ core_rsrc = SC_R_HIFI;
+ aux_core_ram = 0x596f8000;
+ size = SZ_2K;
+ break;
+ default:
+ printf("Not support this core boot up, ID:%u\n", core_id);
+ return -EINVAL;
+ }
+
+ addr = (sc_faddr_t)boot_private_data;
+
+ if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
+ printf("Wrong image address 0x%lx, should not in aux core ram\n",
+ addr);
+ return -EINVAL;
+ }
+
+ printf("Power on aux core %d\n", core_id);
+
+ if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ return -EIO;
+
+ if (mu_rsrc != -1) {
+ if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ return -EIO;
+ }
+
+ if (core_id == 1) {
+ if (sc_pm_clock_enable(ipcHndl, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
+ printf("Error enable clock\n");
+ return -EIO;
+ }
+ if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_SAI_0, SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
+ printf("Error power on SAI0\n");
+ return -EIO;
+ }
+ if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_HIFI_RAM, SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
+ printf("Error power on HIFI RAM\n");
+ return -EIO;
+ }
+ }
+
+ printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
+ if (core_id == 0) {
+ /* M4 use bin file */
+ memcpy((void *)aux_core_ram, (void *)addr, size);
+ } else {
+ /* HIFI use elf file */
+ if (!valid_elf_image(addr))
+ return -1;
+ addr = load_elf_image_shdr(addr);
+ }
+
+ printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
+
+ if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
+ return -EIO;
+
+ printf("bootaux complete\n");
+ return 0;
+}
+#endif
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ sc_rsrc_t core_rsrc;
+ sc_pm_power_mode_t power_mode;
+ sc_ipc_t ipcHndl;
+
+ ipcHndl = gd->arch.ipc_channel_handle;
+
+ switch (core_id) {
+ case 0:
+ core_rsrc = SC_R_M4_0_PID0;
+ break;
+#ifdef CONFIG_IMX8QM
+ case 1:
+ core_rsrc = SC_R_M4_1_PID0;
+ break;
+#endif
+ default:
+ printf("Not support this core, ID:%u\n", core_id);
+ return 0;
+ }
+
+ if (sc_pm_get_resource_power_mode(ipcHndl, core_rsrc, &power_mode) != SC_ERR_NONE)
+ return 0;
+
+ if (power_mode != SC_PM_PW_MODE_OFF)
+ return 1;
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_IMX_SMMU
struct smmu_sid dev_sids[] = {
{ SC_R_SDHC_0, 0x11, "SDHC0" },
#include <command.h>
/* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+static int __arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
{
/* please define platform specific arch_auxiliary_core_up() */
return CMD_RET_FAILURE;
}
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
__attribute__((weak, alias("__arch_auxiliary_core_up")));
/* Allow for arch specific config before we boot */
{
ulong addr;
int ret, up;
+ u32 core = 0;
if (argc < 2)
return CMD_RET_USAGE;
- up = arch_auxiliary_core_check_up(0);
+ if (argc > 2)
+ core = simple_strtoul(argv[2], NULL, 10);
+
+ up = arch_auxiliary_core_check_up(core);
if (up) {
printf("## Auxiliary core is already up\n");
return CMD_RET_SUCCESS;
printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
- ret = arch_auxiliary_core_up(0, addr);
+ ret = arch_auxiliary_core_up(core, addr);
if (ret)
return CMD_RET_FAILURE;
U_BOOT_CMD(
bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
"Start auxiliary core",
- ""
+ "<address> [<core>]\n"
+ " - start auxiliary core [<core>] (default 0),\n"
+ " at address <address>\n"
);
projects / u-boot.git / commitdiff