drm/msm/dpu: Remove unnecessary NULL checks
authorDrew Davenport <ddavenport@chromium.org>
Fri, 6 Dec 2019 23:13:43 +0000 (16:13 -0700)
committerRob Clark <robdclark@chromium.org>
Fri, 3 Jan 2020 00:09:15 +0000 (16:09 -0800)
dpu_hw_ctl* is checked for NULL when passed as an argument
to several functions. It will never be NULL, so remove the
checks.

Signed-off-by: Drew Davenport <ddavenport@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

index 8a6e071..e404bbb 100644 (file)
@@ -1434,7 +1434,7 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
        }
 
        ctl = phys->hw_ctl;
-       if (!ctl || !ctl->ops.trigger_flush) {
+       if (!ctl->ops.trigger_flush) {
                DPU_ERROR("missing trigger cb\n");
                return;
        }
@@ -1484,7 +1484,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
        }
 
        ctl = phys_enc->hw_ctl;
-       if (ctl && ctl->ops.trigger_start) {
+       if (ctl->ops.trigger_start) {
                ctl->ops.trigger_start(ctl);
                trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
        }
@@ -1528,7 +1528,7 @@ static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
        dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
        ctl = phys_enc->hw_ctl;
 
-       if (!ctl || !ctl->ops.reset)
+       if (!ctl->ops.reset)
                return;
 
        DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
@@ -1569,8 +1569,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
                        continue;
 
                ctl = phys->hw_ctl;
-               if (!ctl)
-                       continue;
 
                /*
                 * This is cleared in frame_done worker, which isn't invoked
@@ -1618,7 +1616,7 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
                phys = dpu_enc->phys_encs[i];
 
-               if (phys && phys->hw_ctl) {
+               if (phys) {
                        ctl = phys->hw_ctl;
                        if (ctl->ops.clear_pending_flush)
                                ctl->ops.clear_pending_flush(ctl);
index 0479609..cfd01b0 100644 (file)
@@ -62,7 +62,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
                return;
 
        ctl = phys_enc->hw_ctl;
-       if (!ctl || !ctl->ops.setup_intf_cfg)
+       if (!ctl->ops.setup_intf_cfg)
                return;
 
        intf_cfg.intf = phys_enc->intf_idx;
@@ -125,7 +125,7 @@ static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
 {
        struct dpu_encoder_phys *phys_enc = arg;
 
-       if (!phys_enc || !phys_enc->hw_ctl)
+       if (!phys_enc)
                return;
 
        DPU_ATRACE_BEGIN("ctl_start_irq");
@@ -198,7 +198,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
        u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
        bool do_log = false;
 
-       if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl)
+       if (!phys_enc || !phys_enc->hw_pp)
                return -EINVAL;
 
        cmd_enc->pp_timeout_report_cnt++;
@@ -428,7 +428,7 @@ static void _dpu_encoder_phys_cmd_pingpong_config(
        struct dpu_encoder_phys_cmd *cmd_enc =
                to_dpu_encoder_phys_cmd(phys_enc);
 
-       if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp
+       if (!phys_enc || !phys_enc->hw_pp
                        || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
                DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != 0);
                return;
@@ -458,7 +458,7 @@ static void dpu_encoder_phys_cmd_enable_helper(
        struct dpu_hw_ctl *ctl;
        u32 flush_mask = 0;
 
-       if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) {
+       if (!phys_enc || !phys_enc->hw_pp) {
                DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
                return;
        }
@@ -614,7 +614,7 @@ static int _dpu_encoder_phys_cmd_wait_for_ctl_start(
        struct dpu_encoder_wait_info wait_info;
        int ret;
 
-       if (!phys_enc || !phys_enc->hw_ctl) {
+       if (!phys_enc) {
                DPU_ERROR("invalid argument(s)\n");
                return -EINVAL;
        }
index a83c384..e1d8aeb 100644 (file)
@@ -305,8 +305,6 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
                return;
 
        hw_ctl = phys_enc->hw_ctl;
-       if (!hw_ctl)
-               return;
 
        DPU_ATRACE_BEGIN("vblank_irq");
 
@@ -322,7 +320,7 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
         * so we need to double-check with hw that it accepted the flush bits
         */
        spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
-       if (hw_ctl && hw_ctl->ops.get_flush_register)
+       if (hw_ctl->ops.get_flush_register)
                flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
 
        if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
@@ -566,7 +564,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
        }
 
        ctl = phys_enc->hw_ctl;
-       if (!ctl || !ctl->ops.wait_reset_status)
+       if (!ctl->ops.wait_reset_status)
                return;
 
        /*
@@ -591,7 +589,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
                return;
        }
 
-       if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
+       if (!phys_enc->hw_intf) {
                DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
                                phys_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
                return;