ARM: dts: meson8b: add power domain controller
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Sat, 20 Jun 2020 16:10:10 +0000 (18:10 +0200)
committerKevin Hilman <khilman@baylibre.com>
Mon, 13 Jul 2020 18:56:23 +0000 (11:56 -0700)
The Meson8b SoCs have a power domain controller which can turn on/off
various register areas (such as: Ethernet, VPU, etc.).
Add the main "pwrc" controller and configure the Ethernet power domain.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-4-martin.blumenstingl@googlemail.com
arch/arm/boot/dts/meson8b.dtsi

index ba36168..2069c57 100644 (file)
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/meson8-ddr-clkc.h>
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
+#include <dt-bindings/power/meson8-power.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
        resets = <&reset RESET_ETHERNET>;
        reset-names = "stmmaceth";
+
+       power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
 };
 
 &gpio_intc {
                #clock-cells = <1>;
                #reset-cells = <1>;
        };
+
+       pwrc: power-controller {
+               compatible = "amlogic,meson8b-pwrc";
+               #power-domain-cells = <1>;
+               amlogic,ao-sysctrl = <&pmu>;
+               resets = <&reset RESET_DBLK>,
+                        <&reset RESET_PIC_DC>,
+                        <&reset RESET_HDMI_APB>,
+                        <&reset RESET_HDMI_SYSTEM_RESET>,
+                        <&reset RESET_VENCI>,
+                        <&reset RESET_VENCP>,
+                        <&reset RESET_VDAC_4>,
+                        <&reset RESET_VENCL>,
+                        <&reset RESET_VIU>,
+                        <&reset RESET_VENC>,
+                        <&reset RESET_RDMA>;
+               reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
+                             "venci", "vencp", "vdac", "vencl", "viu",
+                             "venc", "rdma";
+               clocks = <&clkc CLKID_VPU>;
+               clock-names = "vpu";
+               assigned-clocks = <&clkc CLKID_VPU>;
+               assigned-clock-rates = <182142857>;
+       };
 };
 
 &hwrng {