void mxs_set_lcdclk(u32 base_addr, u32 freq);
void select_ldb_di_clock_source(enum ldb_di_clock clk);
void enable_eim_clk(unsigned char enable);
+void mxs_set_vadcclk(void);
int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
#endif /* __ASM_ARCH_CLOCK_H */
}
#endif
+#if defined(CONFIG_VIDEO_GIS)
+void mxs_set_vadcclk()
+{
+ u32 reg = 0;
+
+ reg = readl(&imx_ccm->cscmr2);
+ reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK;
+ reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->cscmr2);
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
{