MLK-20142-2 PCI: imx: refine codes in the initialization

- replace the sleep by the udelay, since it would be used
in the no_irq_suspend/resume callbacks.
- aligned the retries to the PHY_PLL_LOCK_WAIT_MAX_RETRIES

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(Vipul: apply manually while rebase on v4.19)
Signed-off-by: Vipul Kumar <vipul_kumar@mentor.com>

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 48f1e43..6991d88 100644 (file)
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -664,8 +664,7 @@ static int imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
                if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
                        return 0;
 
-               usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
-                            PHY_PLL_LOCK_WAIT_USLEEP_MAX);
+               udelay(PHY_PLL_LOCK_WAIT_USLEEP_MIN);
        }
 
        dev_err(dev, "PCIe PLL lock timeout\n");
@@ -680,7 +679,8 @@ static int imx8_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
        struct device *dev = pci->dev;
 
        if (imx_pcie->variant == IMX8MM) {
-               for (retries = 0; retries < 100; retries++) {
+               for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES;
+                    retries++) {
                        tmp = readl(imx_pcie->phy_base + PCIE_PHY_CMN_REG75);
                        if (tmp == PCIE_PHY_CMN_REG75_PLL_DONE)
                                break;
@@ -688,7 +688,8 @@ static int imx8_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
                }
        } else if (imx_pcie->variant == IMX8QXP
                        || imx_pcie->variant == IMX8QM) {
-               for (retries = 0; retries < 100; retries++) {
+               for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES;
+                               retries++) {
                        if (imx_pcie->hsio_cfg == PCIEAX1PCIEBX1SATA) {
                                regmap_read(imx_pcie->iomuxc_gpr,
                                            IMX8QM_CSR_PHYX2_OFFSET + 0x4,