Clock of spdif tx is derived from clk_ipg and clk_osc, which is not the
integer multiple size of sample rate, can't generate accurate clock for
each sample rate. Use pll4 as the clk_spdif's parent, because the clk_spdif
is the one of source clock of tx, use a proper frequency for pll4, then it
can generate more accurate clock for sample rate (32k,48k,96k,192k).
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
+ assigned-clocks = <&clks IMX6UL_CLK_SPDIF_SEL>,
+ <&clks IMX6UL_CLK_SPDIF_PODF>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <98304000>;
status = "okay";
};
};
};
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <786432000>;
+};
+
&cpu0 {
/*
* on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,