MLK-12027: ARM: dts: fix the sample rate clock not accurate for spdif tx
authorShengjiu Wang <shengjiu.wang@freescale.com>
Wed, 16 Dec 2015 05:16:39 +0000 (13:16 +0800)
committerLeonard Crestez <leonard.crestez@nxp.com>
Wed, 17 Apr 2019 23:31:07 +0000 (02:31 +0300)
Clock of spdif tx is derived from clk_ipg and clk_osc, which is not the
integer multiple size of sample rate, can't generate accurate clock for
each sample rate. Use pll4 as the clk_spdif's parent, because the clk_spdif
is the one of source clock of tx, use a proper frequency for pll4, then it
can generate more accurate clock for sample rate (32k,48k,96k,192k).

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-spdif.dts
arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts

index ee53073..7191f05 100644 (file)
@@ -34,5 +34,9 @@
 &spdif {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spdif>;
+       assigned-clocks = <&clks IMX6UL_CLK_SPDIF_SEL>,
+                         <&clks IMX6UL_CLK_SPDIF_PODF>;
+       assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+       assigned-clock-rates = <0>, <98304000>;
        status = "okay";
 };
index d31bd3c..1257352 100644 (file)
        };
 };
 
+&clks {
+       assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+       assigned-clock-rates = <786432000>;
+};
+
 &cpu0 {
        /*
         * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,