MLK-12495 mx6: Add LDO bypass support to i.MX6 SOC

Port LDO bypass SOC codes from v2017 to support the features:

1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
   enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
   on the flatten device tree file.

2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
   on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
   reboot whole board, so split these code to independent function so that board file
   can call it freely.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 6bceaf009718cec856e11106d26e13601631fa4f)
(cherry picked from commit 0e2de4c2d5d2c79e485d164394f03065743ba2c4)
(cherry picked from commit 4160d7362893873d04b8a2d618ad6ff84c411da4)

diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 1e5fa1a..688aabf 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -38,4 +38,15 @@ static inline void iomuxc_set_rgmii_io_voltage(int io_vol)
        __raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII);
 }
 
+void set_wdog_reset(struct wdog_regs *wdog);
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+int check_ldo_bypass(void);
+int check_1_2G(void);
+int set_anatop_bypass(int wdog_reset_pin);
+void ldo_mode_set(int ldo_bypass);
+void prep_anatop_bypass(void);
+void finish_anatop_bypass(void);
+#endif
+
 #endif /* __SYS_PROTO_IMX6_ */

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 38b87ed..9dfbcce 100644 (file)
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -302,6 +302,9 @@ void arch_preboot_os(void)
 #endif
        }
 #endif
+#if defined(CONFIG_LDO_BYPASS_CHECK)
+       ldo_mode_set(check_ldo_bypass());
+#endif
 #if defined(CONFIG_VIDEO_IPUV3)
        /* disable video before launching O/S */
        ipuv3_fb_shutdown();

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 92fb4c4..af91d33 100644 (file)
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -107,6 +107,14 @@ config MX6_DDRCAL
          Say "Y" if your board uses dynamic (per-boot) DDR calibration.
          If unsure, say N.
 
+config LDO_BYPASS_CHECK
+       bool "Enable the LDO bypass checking and setting"
+       default y if !MX6SLL
+       help
+         This feature searches the gpc node in loaded DTB and checking the
+         "fsl,ldo-bypass" property. When the property is set, board relevant 
+         PMIC settings are called to adjust for LDO bypass. 
+
 choice
        prompt "MX6 board select"
        optional

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index c4e4df8..c3a441b 100644 (file)
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -600,6 +600,28 @@ const struct boot_mode soc_boot_modes[] = {
 };
 #endif
 
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+       u32 reg = readw(&wdog->wcr);
+       /*
+        * use WDOG_B mode to reset external pmic because it's risky for the
+        * following watchdog reboot in case of cpu freq at lowest 400Mhz with
+        * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
+        * in ldo-bypass mode watchdog reset will only triger POR reset, not
+        * WDOG reset. But below code depends on hardware design, if HW didn't
+        * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
+        * these code since it assumed boot from 400Mhz always.
+        */
+       reg = readw(&wdog->wcr);
+       reg |= 1 << 3;
+       /*
+        * WDZST bit is write-once only bit. Align this bit in kernel,
+        * otherwise kernel code will have no chance to set this bit.
+        */
+       reg |= 1 << 0;
+       writew(reg, &wdog->wcr);
+}
+
 void reset_misc(void)
 {
 #ifndef CONFIG_SPL_BUILD
@@ -779,3 +801,122 @@ void gpr_init(void)
                writel(0x007F007F, &iomux->gpr[7]);
        }
 }
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+DECLARE_GLOBAL_DATA_PTR;
+static int ldo_bypass;
+
+int check_ldo_bypass(void)
+{
+       const int *ldo_mode;
+       int node;
+
+       /* get the right fdt_blob from the global working_fdt */
+       gd->fdt_blob = working_fdt;
+       /* Get the node from FDT for anatop ldo-bypass */
+       node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+               "fsl,imx6q-gpc");
+       if (node < 0) {
+               printf("No gpc device node %d, force to ldo-enable.\n", node);
+               return 0;
+       }
+       ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL);
+       /*
+        * return 1 if "fsl,ldo-bypass = <1>", else return 0 if
+        * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property
+        */
+       ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0;
+
+       return ldo_bypass;
+}
+
+int check_1_2G(void)
+{
+       u32 reg;
+       int result = 0;
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       struct fuse_bank *bank = &ocotp->bank[0];
+       struct fuse_bank0_regs *fuse_bank0 =
+                       (struct fuse_bank0_regs *)bank->fuse_regs;
+
+       reg = readl(&fuse_bank0->cfg3);
+       if (((reg >> 16) & 0x3) == 0x3) {
+               if (ldo_bypass) {
+                       printf("Wrong dtb file used! i.MX6Q@1.2Ghz only "
+                               "works with ldo-enable mode!\n");
+                       /*
+                        * Currently, only imx6q-sabresd board might be here,
+                        * since only i.MX6Q support 1.2G and only Sabresd board
+                        * support ldo-bypass mode. So hardcode here.
+                        * You can also modify your board(i.MX6Q) dtb name if it
+                        * supports both ldo-bypass and ldo-enable mode.
+                        */
+                       printf("Please use imx6q-sabresd-ldo.dtb!\n");
+                       hang();
+               }
+               result = 1;
+       }
+
+       return result;
+}
+
+static int arm_orig_podf;
+void set_arm_freq_400M(bool is_400M)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       if (is_400M)
+               writel(0x1, &mxc_ccm->cacrr);
+       else
+               writel(arm_orig_podf, &mxc_ccm->cacrr);
+}
+
+void prep_anatop_bypass(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       arm_orig_podf = readl(&mxc_ccm->cacrr);
+       /*
+        * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo
+        * bypassed, also downgrade internal vddarm ldo to 0.975V.
+        * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V)
+        * otherwise at 800Mhz(i.mx6dl):
+        * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V)
+        * We need provide enough gap in this case.
+        * skip if boot from 400M.
+        */
+       if (!arm_orig_podf)
+               set_arm_freq_400M(true);
+
+       if (!is_mx6dl() && !is_mx6sx())
+               set_ldo_voltage(LDO_ARM, 975);
+       else
+               set_ldo_voltage(LDO_ARM, 1150);
+}
+
+int set_anatop_bypass(int wdog_reset_pin)
+{
+       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       struct wdog_regs *wdog;
+       u32 reg = readl(&anatop->reg_core);
+
+       /* bypass VDDARM/VDDSOC */
+       reg = reg | (0x1F << 18) | 0x1F;
+       writel(reg, &anatop->reg_core);
+
+       if (wdog_reset_pin == 2)
+               wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
+       else if (wdog_reset_pin == 1)
+               wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
+       else
+               return arm_orig_podf;
+       set_wdog_reset(wdog);
+       return arm_orig_podf;
+}
+
+void finish_anatop_bypass(void)
+{
+       if (!arm_orig_podf)
+               set_arm_freq_400M(false);
+}
+#endif