MLK-17120: arm64: dts: assign the clock rate for GPMI NAND in DT

Assign the clock rate for GPMI NAND on i.MX8QXP ARM2 device tree.

To keep the same clock rate after system suspend/resume, we need to set
assign a clock rate for GPMI NAND, otherwise the timing register won't
match with the clock setting.

The code change also a workaround for SCU clock rate setting. NAND use a
very low clock freq (22Mhz) and safe timing to identify which chips were
connected. This low freq divide from high freq parent clock(1Ghz) caused
the SCU clock divider go beyond the limit (31)

SCU need to implement the clk_round_rate to found this issue and return
error value to upper layer. Right now assign 50Mhz for GPMI initial
clock as a workaround.

Signed-off-by: Han Xu <han.xu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 40a50d6..2cbc9c3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -1647,6 +1647,8 @@
                dmas = <&dma_apbh 0>;
                dma-names = "rx-tx";
                power-domains = <&pd_conn_nand>;
+               assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>;
+               assigned-clock-rates = <50000000>;
                status = "disabled";
        };