MLK-11508-3: imx6qdl: add csi mux setting

Add CSI mux setting

Signed-off-by: Sandor Yu <R01008@freescale.com>

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 08f0639..13e8e28 100644 (file)
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -229,6 +229,35 @@ put_node:
        of_node_put(np);
 }
 
+static void __init imx6q_csi_mux_init(void)
+{
+       /*
+        * MX6Q SabreSD board:
+        * IPU1 CSI0 connects to parallel interface.
+        * Set GPR1 bit 19 to 0x1.
+        *
+        * MX6DL SabreSD board:
+        * IPU1 CSI0 connects to parallel interface.
+        * Set GPR13 bit 0-2 to 0x4.
+        * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1.
+        * Set GPR13 bit 3-5 to 0x1.
+        */
+       struct regmap *gpr;
+
+       gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+       if (!IS_ERR(gpr)) {
+               if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
+                       of_machine_is_compatible("fsl,imx6q-sabreauto"))
+                       regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19);
+               else if (of_machine_is_compatible("fsl,imx6dl-sabresd") ||
+                        of_machine_is_compatible("fsl,imx6dl-sabreauto"))
+                       regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C);
+       } else {
+               pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",
+                      __func__);
+       }
+}
+
 static void __init imx6q_axi_init(void)
 {
        struct regmap *gpr;
@@ -379,6 +408,7 @@ static void __init imx6q_init_machine(void)
 
        imx6q_enet_init();
        imx_anatop_init();
+       imx6q_csi_mux_init();
        cpu_is_imx6q() ?  imx6q_pm_init() : imx6dl_pm_init();
        imx6q_axi_init();
 }