reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
- domain-id = <0>;
#power-domain-cells = <0>;
domain-name = "HSIO_PD";
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>,
pcie0_pd: power-domain@1 {
reg = <1>;
- domain-id = <1>;
#power-domain-cells = <0>;
domain-name = "PCIE0_PD";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
usb_otg1_pd: power-domain@2 {
reg = <2>;
- domain-id = <2>;
#power-domain-cells = <0>;
domain-name = "USB_OTG1_PD";
};
usb_otg2_pd: power-domain@3 {
reg = <3>;
- domain-id = <3>;
#power-domain-cells = <0>;
domain-name = "USB_OTG2_PD";
};
gpumix_pd: power-domain@4 {
compatible = "fsl,imx8mm-pm-domain";
reg = <4>;
- domain-id = <4>;
#power-domain-cells = <0>;
domain-name = "GPUMIX_PD";
clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
- domain-id = <5>;
#power-domain-cells = <0>;
domain-name = "VPUMIX_PD";
clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
vpu_g1_pd: power-domain@6 {
reg = <6>;
- domain-id = <6>;
#power-domain-cells = <0>;
domain-name = "VPU_G1_PD";
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
vpu_g2_pd: power-domain@7 {
reg = <7>;
- domain-id = <7>;
#power-domain-cells = <0>;
domain-name = "VPU_G2_PD";
clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
vpu_h1_pd: power-domain@8 {
reg = <8>;
- domain-id = <8>;
#power-domain-cells = <0>;
domain-name = "VPU_H1_PD";
clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>;
reg = <9>;
#address-cells = <1>;
#size-cells = <0>;
- domain-id = <9>;
#power-domain-cells = <0>;
domain-name = "DISPMIX_PD";
clocks = <&clk IMX8MM_CLK_DISP_ROOT>;
mipi_pd: power-domain@10 {
reg = <10>;
- domain-id = <10>;
#power-domain-cells = <0>;
domain-name = "MIPI_PD";
};
compatible = "fsl,imx8mq-pm-domain";
reg = <0>;
#power-domain-cells = <0>;
- domain-id = <0>;
domain-name = "MIPI_PD";
};
compatible = "fsl,imx8mq-pm-domain";
reg = <1>;
#power-domain-cells = <0>;
- domain-id = <1>;
domain-name = "PCIE0_PD";
};
compatible = "fsl,imx8mq-pm-domain";
reg = <2>;
#power-domain-cells = <0>;
- domain-id = <2>;
domain-name = "USB_OTG1_PD";
};
compatible = "fsl,imx8mq-pm-domain";
reg = <3>;
#power-domain-cells = <0>;
- domain-id = <3>;
domain-name = "USB_OTG2_PD";
};
compatible = "fsl,imx8mq-pm-domain";
reg = <4>;
#power-domain-cells = <0>;
- domain-id = <4>;
domain-name = "GPU_PD";
clocks = <&clk IMX8MQ_CLK_GPU_AXI>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
<&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_AHB>;
compatible = "fsl,imx8mq-pm-domain";
reg = <5>;
#power-domain-cells = <0>;
- domain-id = <5>;
domain-name = "VPU_PD";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
compatible = "fsl,imx8mq-pm-domain";
reg = <8>;
#power-domain-cells = <0>;
- domain-id = <8>;
domain-name = "MIPI_CSI1_PD";
};
compatible = "fsl,imx8mq-pm-domain";
reg = <9>;
#power-domain-cells = <0>;
- domain-id = <9>;
domain-name = "MIPI_CSI2_PD";
};
compatible = "fsl,imx8mq-pm-domain";
reg = <10>;
#power-domain-cells = <0>;
- domain-id = <10>;
domain-name = "PCIE1_PD";
};
};